Lateral diffusion type low on resistance MOS (metal oxide semiconductor) device

Abstract

The invention discloses a lateral diffusion type low on resistance MOS (metal oxide semiconductor) device, which comprises a P-type trap layer and an N-type light doped layer, wherein the P-type trap layer is positioned in a P-type substrate layer; a gate electrode region is positioned above a gate oxide layer; at least two grooves are arranged between a source electrode region and the N-type light doped layer and are positioned on the upper part of the P-type trap layer; the etching depth of the groove near the source electrode region is less than the etching depth of the groove near the N-type light doped layer; the etching depths of the plurality of grooves are successively increased from the source electrode region to the N-type light doped layer; a P-type light doped region is arranged in the N-type light doped layer; the P-type light doped region is positioned in the middle region of the horizontal direction of the N-type light doped layer; and the P-type light doped region is positioned in the middle region of the vertical direction of the N-type light doped layer. In the above mode, according to the lateral diffusion type low on the resistance MOS device, which is disclosed by the invention, the breakdown resistance voltage can be improved, the device ratio on resistance is lowered, the response time and the frequency characteristic are improved, the integral performance is optimized, and the size is reduced.

Description

technical field [0001] The invention relates to a MOS device, in particular to a lateral diffusion low conduction resistance MOS device. Background technique [0002] Metal oxide power MOS semiconductor devices, with the rapid development of the semiconductor industry, power electronics technology represented by high-power semiconductor devices has developed rapidly, and its application fields have continued to expand, such as the control of AC motors and printer drive circuits. Among various power devices today, the laterally diffused MOS semiconductor device LDMOS has a high operating voltage and a relatively simple process, so the LDMOS has broad development prospects. In the design of LDMOS devices, the breakdown voltage and on-resistance have always been the main goals that people pay attention to when designing such devices. The thickness of the epitaxial layer, doping concentration, and the length of the drift region are the most important parameters of LDMOS. The br...

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Problems solved by technology

[0003] With the development of device miniaturization, the existing LDMOS design occupies a large layout area, which is not conducive to its integration with other functional devices to further reduce the volume and expand the application range. Therefore, how to design a device that can effectively reduce the current Some LDMOS occupy the surface area of ​​the silicon wafer and can further improve the performance of the device, becoming a technical obstacle

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