Method for preparing h-BN medium graphene integrated circuits on large scale

Abstract

The invention belongs to the field of semiconductor devices and semiconductor processes, and aims to provide a method for preparing h-BN medium graphene integrated circuits on a large scale. In the method, a catalytic metal layer is subjected to photoetching by using the characteristic of selective growth of h-BN and graphene on a catalytic metal substrate, and control on the patterns of an h-BN layer and a graphene layer growing in an epitaxial way is realized, so that large-scale manufacturing of graphene field effect transistors taking the h-BN as a medium is realized. According to the method, the problems of high process difficulty, low yield and poor performance in the large-scale preparation process of graphene devices are solved, and a good basis is laid for the preparation of the graphene-based integrated circuits.

Description

Technical field:

[0001] The invention relates to a h-BN dielectric graphene integrated circuit manufacturing technology, in particular to a large-scale manufacturing technology of a double-gate graphene field effect transistor using h-BN as a dielectric. Background technique:

[0002] Graphene is a two-dimensional material with extremely excellent performance formed by carbon atoms in a hexagonal honeycomb lattice. Its carrier velocity and mobility are much higher than conventional semiconductor materials. It is considered as an integrated circuit material in the post-silicon era. Currently, large-scale graphene wafers can be grown by CVD on catalytic metal substrates and SiC epitaxy. In the preparation of graphene electronic devices, either the graphene prepared by CVD method needs to be transferred to SiO 2 / Si (or other) substrates, or directly use the 6H-SiC substrate as the dielectric layer. These substrates not only have a certain surface roughness, but also have a la...

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