44results about How to "Improved lattice structure" patented technology

Atomic Layer Deposition (ALD) is used for heteroepitaxial film growth at reaction temperatures ranging from 80-400° C. The substrate and film materials are preferably selected to take advantage of Domain Matched Epitaxy (DME). A laser annealing system is used to thermally anneal deposition layers after deposition by ALD. In preferred embodiments a silicon substrate is overlaid with an AIN nucleation layer and laser annealed. Thereafter a GaN device layers is applied over the AIN layer by an ALD process and then laser annealed. In a further example embodiment a transition layer is applied between the GaN device layer and the AIN nucleation layer. The transition layer comprises one or more different transition material layers each comprising a AlxGa1-x compound wherein the composition of the transition layer is continuously varied from AIN to GaN.

The present invention relates generally to improved lattice structures that can be used in, for example, blast resistant armor appliqués. In another embodiment, the present invention relates to methods for designing improved lattice structures where the lattice structures are bistable bond lattice structures. In still another embodiment, the present invention relates to lattice structures that employ asymmetric waiting links and unequal lengths of main links.

Atomic Layer Deposition (ALD) is used for heteroepitaxial film growth at reaction temperatures ranging from 80-400° C. The substrate and film materials are preferably matched to take advantage of Domain Matched Epitaxy (DME). A laser annealing system is used to thermally anneal deposition layer after deposition by ALD. In preferred embodiments, a silicon substrate is overlaid with an AlN nucleation layer and laser annealed. Thereafter a GaN device layer is applied over the AlN layer by an ALD process and then laser annealed. In a further example embodiment, a transition layer is applied between the GaN device layer and the AlN nucleation layer. The transition layer comprises one or more different transition material layers each comprising a AlxGa1-xN compound wherein the composition of the transition layer is continuously varied from AlN to GaN.

The invention discloses a large-size graphene stack structure wafer which is characterized in that a wafer structure comprises a graphene single crystal layer, an h-BN (hexagonal boron nitride) single crystal layer, an h-BN buffer layer and SiO2 / Si wafer substrates from the top down sequentially. The wafer and the preparation method have the benefits that the wafer can be compatible with a production technique of the available silicon substrate semiconductor device sufficiently, and can take full advantage of the characteristic of a hexagonal boron nitride substrate material; growing graphene has a most perfect crystal structure and a carrier transport environment with the weakest scattering; the super-high mobility of carriers in graphene is kept at the utmost; and the performance of a graphene substrate electronic device is improved greatly.

A method for reducing series resistance for transistors includes forming a conductive gate over and insulated from a semiconductor substrate, forming source and / or drain extension regions within the substrate and adjacent to respective source and / or drain regions, and forming source and / or drain regions within the substrate. The source and / or drain extension regions are formed from a material alloyed with a first dopant and a second dopant, the first dopant configured to increase a lattice structure of the material forming the source and / or drain extension regions.

The invention provides a formation method of a semiconductor device. The formation method of a semiconductor device comprises the steps: providing a substrate with isolation structures; forming a gate structure on the surface of part of the substrate between the adjacent isolation structures; forming a groove exposing the side wall of the isolation structure in the substrate at two sides of each gate structure; nitriding the side wall of the exposed isolation structure, and forming an anti-corrosion layer on the surface of the side wall of the isolation structure; after forming the anti-corrosion layer, cleaning the surface of the bottom and the side wall of the groove; and forming a stress layer filling the groove. The formation method of a semiconductor device can prevent cleaning from etching the isolation structure so as to enable the isolation structure to maintain good shape and provide good interface performance for forming the stress layer, and can enable the isolation structure to maintain good electrical isolation performance and can optimize the electrical properties for the formed semiconductor device.