A kind of semiconductor packaging structure and preparation method thereof

Abstract

The invention provides a semiconductor package structure and a preparation method thereof. The semiconductor package structure includes: a metal interconnection layer on a semiconductor substrate; a metal shielding layer on the metal interconnection layer; a pad layer on the metal shielding layer; the metal shielding layer is a multilayer A superimposed structure, the coefficients of thermal expansion of each layer in the multi-layer superimposed structure decrease gradually from bottom to top. The semiconductor packaging structure has good thermodynamic properties, which can effectively reduce the difference in volume change of the metal interconnect layer and the metal shielding layers caused by thermal expansion and contraction after the annealing process of the semiconductor packaging structure preparation, and thus The probability of cracking at the crystalline interface of each layer caused by it, so as to avoid the phenomenon of pad peeling. Moreover, the metal shielding layer of the multi-layer stacked structure has better mechanical properties, which can alleviate the damage to the active area of ​​the semiconductor device caused by various stresses generated by the welding and wire bonding process.

Description

technical field [0001] The invention relates to the field of semiconductor preparation, in particular to a semiconductor packaging structure and a preparation method thereof. Background technique [0002] With the continuous improvement of semiconductor manufacturing technology and the continuous reduction of gate size in transistors, the size of integrated circuit devices is continuously reduced, and a large number of semiconductor elements are densely embedded in the chip substrate with a multi-layer interconnection structure, and through multi-layer Metal interconnect layer connection. In the existing semiconductor technology, copper is the most commonly used wiring for metal interconnection layers due to its good electrical conductivity. For specific technology, please refer to the Chinese patent application with publication number CN1881557A. [0003] In the back end of line (BEOL) of semiconductor device fabrication, welding and wire bonding technology is a widely use...

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Problems solved by technology

[0007] However, it is found in actual operation that regardless of the single layer (generally using TaN layer, which has a strong ability to prevent copper-aluminum diffusion) or the multi-layer metal shielding layer structure, the metal shielding layer has the same effect on the ability to prevent copper-aluminum diffusion. It is proportional to the thickness (the current TaN layer is generally about 700A), but too thick TaN is connected to the interconnection metal in the wire bonding strength test, and the pad peeling phenomenon often occurs, which greatly reduces the yield of semiconductor chip packaging. , and cause performance problems for subsequent packaged semiconductor chips

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