SOI horizontal power MOSFET device

Abstract

The invention provides an SOI horizontal power MOSFET device and belongs to the technical field of power semiconductor devices. A dielectric groove is introduced in a drift region and filled with two or more dielectric materials, and the dielectric coefficients of the dielectric materials are lower than the dielectric coefficient of an active layer and are gradually decreased from bottom to top; the side, close to a body region, of the dielectric groove is of a body region longitudinal extension structure; a semiconductor buried layer opposite to the drift region in doping type is arranged between the dielectric groove and a dielectric buried layer. Because the dielectric groove filled with the variable k dielectric materials has an modulating action on an internal electric field of the active layer and plays a role in longitudinally folding the drift region, the voltage resistance of the device is greatly improved, and the horizontal size of the device is reduced; because of introduction of the body region longitudinal extension structure and the semiconductor buried layer, the voltage resistance of the device is further improved, the exhausting action on the drift region is enhanced, the doping concentration of the drift region can be improved, and therefore the on resistance of the device is reduced; the grid and drain capacitance of the device can be further reduced through the dielectric groove, and the frequency and output power of the device are improved.

Description

technical field [0001] The invention belongs to the technical field of power semiconductor devices, and relates to MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor, Metal-Oxide-Semiconductor Field-Effect Transistor) devices, especially SOI (Semiconductor On Insulator, semiconductor on insulating layer) MOSFET device Background technique [0002] For conventional LDMOS devices, the length of the drift region increases monotonically with the breakdown voltage of the device. This not only increases the chip area and cost of the device (or circuit), but also is not conducive to the miniaturization of integrated circuits. More seriously, the on-resistance of the device increases with the increase of the length of the drift region (or the withstand voltage of the device) (the relationship between the on-resistance and the withstand voltage of the device can be expressed as: R on,sp ∝BV 2.5 , where BV is the device withstand voltage, R on,sp is the specific on-resistan...

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Problems solved by technology

When the withstand voltage of the device is higher than 300V, on the one hand, this type of device requires a thicker active layer, which will inevitably lead to increased difficulty in the process of extending the trench gate 8, resulting in an increase in cost; on the other hand, a thicker dielectric buried layer 2, which will lead to serious self-heating effects; in addition, in high-voltage applications, the channel resistance accounts for a small proportion of the total device resistance, and the use of dual channels increases the process complexity, but does not improve the on-resistance of the device. Big

It can be seen that this type of device is not suitable for manufacturing power devices with a withstand voltage >300V

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