Radiation resistant layout and wiring method of integrated circuit

Abstract

The invention belongs to the field of integrated circuits, and relates to an anti-radiation placing and routing method for integrated circuits. According to the method, the possibility of diffusing a wrong trigger storage value to other triggers through a combinational circuit or directly diffusing the wrong trigger storage value to the other triggers is reduced through decreasing the float time of signal transmission among the triggers, so that the anti-radiation performance of the whole circuits is improved. According to the method, the anti-radiation ability is improved through decreasing the float time of the signal transmission, so that the target clock frequency is not reduced and the performance loss of the whole circuits is small. According to the method, a proper amount of buffers are inserted according to a constraint condition, but the circuit structures of the triggers are not changed, the quantity of the triggers is not increased or other redundant circuits are not added, so that the area overhead is small. The anti-radiation placing and routing method for integrated circuits is not only capable of strengthening the anti-radiation ability of the non-hardened circuits, but also capable of furthermore improving the anti-radiation ability of the hardened circuits.

Description

technical field [0001] The invention belongs to the field of integrated circuits, and in particular relates to a radiation-resistant layout and wiring method for integrated circuits. Background technique [0002] As the size of the process decreases, the integrated circuits in the chip are more and more susceptible to errors caused by heavy particle or proton radiation in high-level space or near-Earth space. Studies have shown that if radiation occurs at a combinational circuit node, it may cause a single-event transient pulse and change the logic state of the circuit node; the error value caused by the single-event transient pulse is only transmitted to the trigger near the rising edge (or falling edge) of the clock. The flip-flop will be captured and stored, so the possibility of the transient error pulse of the combination circuit affecting the flip-flop is not very high, but if the radiation occurs at the storage node of the flip-flop, it may directly cause the flip-flo...

AI Technical Summary

Problems solved by technology

[0003] The design methods of radiation-hardened integrated circuits in the prior art mainly include multi-mode redundancy, error correction codes, radiation-resistant storage units, and radiation-resistant layout and wiring methods; among them, the multi-mode redundancy method is based on the triple-mode redundancy technology[2] As a representative, redundant circuit modules and majority voting circuits are used to shield the output of wrong circuit modules, but this method will bring a large area overhead; the error correction code method is represented by Hamming code [3], by calculating the correction code check value to locate the position of the wrong bit; the radiation-resistant memory cell method is represented by the double interlocked memory cell [4], which adds additional transistors and intertwisted interconnection lines on the basis of the basic memory cell structure to enhance the security of sensitive nodes. Radiation resistance, but the error correction code and radiation-resistant storage unit will bring a large area overhead and reduce circuit performance; the radiation-resistant layout and routing method enhances the overall circuit by adjusting the position of each standard unit circuit and the interconnection path. Radiation resistance, this method has small area overhead and performance loss, but the current radiation-resistant layout and routing method is mainly aimed at field programmable gate arrays, represented by literature [5], to reduce the number of connections in programmable interconnection code points Possibility of short circuit, open circuit and bridging error, this type of radiation-hard layout and routing method for general IC field programmable gate array cannot be used for ASIC, because ASIC has specific functions, and there is no programmable interconnection code point