Fabrication method of vertical-structure blue-light LED chip

An LED chip, vertical structure technology, applied in electrical components, circuits, semiconductor devices, etc., can solve the problems of restricting the working current of LED chips, working current limitation, long heat conduction path, etc., to improve photoelectric efficiency, device efficiency, The effect of improved heat dissipation

Active Publication Date: 2017-02-22
CHINA UNITED NORTHWEST INST FOR ENG DESIGN & RES
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, this P-type contact structure restricts the working current of the LED chip
On the other hand, the PN junction heat of this structure is exported through the sapphire substrate. In view o

Method used

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  • Fabrication method of vertical-structure blue-light LED chip
  • Fabrication method of vertical-structure blue-light LED chip
  • Fabrication method of vertical-structure blue-light LED chip

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preparation example Construction

[0056] see figure 1 As shown, the present invention discloses a method for preparing a vertical structure blue LED chip. The substrate with a low-stress buffer layer is used as the growth basis, and then other layers of epitaxy are sequentially grown on the flat u-GaN surface to prepare the Blue LED epitaxial wafer; finally, the blue LED epitaxial wafer is made into a vertical structure LED, which mainly includes the following steps: depositing a reflector on the surface of the LED epitaxial wafer, and making a metal electrode pattern, using a high-temperature metal bonding process to bond the metal electrode pattern surface It is bonded on the metal substrate, and the substrate is peeled off by laser lift-off technology; another metal electrode pattern is made on the surface of u-GaN.

[0057] The bonding process is to prepare the bonding layer material on the surface of the wafer to be bonded, then stick the two wafers together and use external energy to form a covalent bond...

Embodiment 1

[0079] First prepare the purple LED epitaxial wafer, including the following steps:

[0080] 1.1) Baking with N2 at 1070°C and pressure of 150torr for 10min to nitride the sapphire, SiC or Si substrate;

[0081] 1.2) Cool down the sapphire, SiC or Si substrate after nitriding in step 1 to 515°C and a pressure of 800torr, then grow a low-stress buffer layer with a thickness of 0.8μm on the substrate, then raise the temperature to 1030°C and a pressure of 400torr Recrystallize the low-stress buffer layer and re-grow a 0.8μm N-type roughening layer;

[0082] 1.3) Raise the temperature to 1070°C and the pressure to 200torr to grow a lightly Si-doped N-type electrode layer with a thickness of 0.8μm, and then grow a heavily Si-doped N-type GaN layer with a thickness of 1.8μm;

[0083] 1.4) growing an n-GaN electron diffusion layer on the basis of the N-type GaN layer, with a thickness of 80nm; growing a stress release layer on the n-GaN electron diffusion layer, with a thickness of...

Embodiment 2

[0100] First prepare the purple LED epitaxial wafer, including the following steps:

[0101] 1.1) Bake the sapphire, SiC or Si substrate at a temperature of 1080°C and a pressure of 150 torr for 20 minutes with N2;

[0102] 1.2) Lower the temperature of the sapphire, SiC or Si substrate after nitriding in step 1 to 525°C and a pressure of 800torr, then grow a low-stress buffer layer with a thickness of 1μm on the substrate, then raise the temperature to 1040°C and a pressure of 400torr to make The low-stress buffer layer is recrystallized, and a 0.9μm N-type roughening layer is regrown;

[0103] 1.3) Raise the temperature to 1080°C and the pressure to 200torr to grow a lightly Si-doped N-type electrode layer with a thickness of 0.8μm, and then grow a heavily Si-doped N-type GaN layer with a thickness of 2.1μm;

[0104] 1.4) growing an n-GaN electron diffusion layer on the basis of the N-type GaN layer, with a thickness of 100 nm; growing a stress release layer on the n-GaN el...

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Abstract

The invention discloses a fabrication method of a vertical-structure blue-light LED chip. The fabrication method comprises the steps of firstly, taking a substrate with a low stress buffer layer as a growth foundation; secondly, sequentially growing other epitaxial layers on a smooth u-GaN surface to obtain a blue-light LED epitaxial wafer; and finally, fabricating a vertical-structure LED from the blue-light LED epitaxial wafer, wherein the step of fabricating the vertical-structure LED mainly comprises the following steps of depositing and forming a reflecting mirror on a surface of the LED epitaxial wafer, fabricating a metal electrode pattern, bonding a surface of the metal electrode pattern on a metal substrate by a high-temperature metal bonding process, stripping the substrate by a laser lift-off technology, and fabricating another metal electrode pattern on the u-GaN surface. The vertical-structure LED fabricated according to the method is relatively high in single-chip power, the quantity of LEDs in series and in parallel is reduced, the user demand can be satisfied by a single chip, meanwhile, a driving circuit design is simplified, the reliability of an LED product is greatly improved, and the service lifetime of the LED product is greatly prolonged.

Description

[0001] 【Technical field】 [0002] The invention belongs to the technical field of semiconductors, and in particular relates to a method for preparing a vertical structure blue LED chip. [0003] 【Background technique】 [0004] The application of semiconductor lighting has accelerated significantly in recent years, and its effect has been recognized by the market, but its penetration rate in the entire lighting market is still low. The domestic LED lighting application market has not yet become the leading force in industrial development. The semiconductor lighting application market, especially the functional lighting market is in the initial stage of development, with huge future space. [0005] For traditional front-mounted LED chips, P-type GaN is difficult to dope, resulting in low hole carrier concentration and difficulty in growing thick, resulting in difficult diffusion of current. At present, the method of preparing ultra-thin metal film or ITO film on the surface of P...

Claims

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Application Information

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IPC IPC(8): H01L33/00H01L33/64
CPCH01L33/007H01L33/0093H01L33/641
Inventor 田伟刘波波田进赵俊李谊
Owner CHINA UNITED NORTHWEST INST FOR ENG DESIGN & RES
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