Serial communication clock data recovery system with low sampling rate

Abstract

The invention discloses a serial communication clock data recovery system and relates to the field of high-speed serial communication systems. Sampling data passes through an Alexander phase discriminator with the 1 / 4 rate, the phase position relations of the data and eight phase clocks are compared, UP and DN signals control a charge pump to discharge, and then through a comparator and a counter, a phase selection / phase interpolation circuit is controlled. The phase selection / phase interpolation circuit carries out selection and interpolation operation on eight phase reference clocks, a pair of orthogonal clocks are output to enter a delay phase-locked loop, and the delay phase-locked loop generates the eight phase clocks to sample input data respectively until the four phase clocks of the eight phase sampling clocks are aligned with the jumping edge of the data; then the remaining four phase clocks are aligned with the middle of the data at the moment and are recovered data sampling clocks; the frequency of the sampling clocks is lowered and is 1 / 4 the frequency of the data, in this way, the design of a clock circuit is simplified, and meanwhile the dynamic power consumption of the circuit is lowered.

Description

technical field [0001] The invention relates to the field of high-speed serial communication systems, in particular to a low sampling rate serial communication clock data recovery system. Background technique [0002] In a high-speed serial communication system, due to the influence of noise, the data will be delayed or distorted in amplitude during transmission. Therefore, the data needs to be repositioned at the receiving end, that is, clock data recovery. The receiver of serial communication receives the attenuated input serial signal, and needs to extract the clock information according to its transition edge information, and the state of the data phase can be estimated from the extracted clock information. Since the clock information is hidden in the serial data to be transmitted, the clock and data recovery circuit in the receiving channel must adopt a specific algorithm, which can correctly adjust the phase of the local sampling clock according to the phase difference...

AI Technical Summary

Problems solved by technology

[0003] The existing clock data recovery circuit generally adopts a full-rate or half-rate structure. When recovering high-speed serial data, the frequency of the sampling clock is high, which increases the difficulty of clock circuit design.

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