A Capacitance Sorting Method for Improving the Linearity of Resistor-Capacitor Successive Approximation Analog-to-Digital Converters

Abstract

The invention discloses a capacitance sorting method capable of improving the linearity of the resistance-capacitance successive approximation analog-to-digital converter, which belongs to the successive approximation analog-to-digital converter and is applied to high-speed and high-precision analog-to-digital converters in the fields of microelectronics and solid-state electronics . This method does not require the introduction of any correction algorithm, only the ordering and reconstruction of the capacitances. The capacitance sorting method proposed in the present invention can avoid the accumulation of capacitance mismatch errors in the same code word. Therefore, compared with the traditional correction method that relies on correction algorithms to improve linearity, it has simpler structure, smaller chip area, and more Effects that are easy to implement on-chip.

Description

technical field [0001] The invention relates to a successive approximation analog-to-digital converter, which is a high-speed and high-precision analog-to-digital converter used in the fields of microelectronics and solid-state electronics. Background technique [0002] In recent years, the development of information technology has led to the rapid development of technologies such as portable medical instruments, communications industry, security inspection systems, high-performance computing, biomedicine, and digital signal processing, leading to the rapid development of radar, communications, electronic countermeasures, aerospace, measurement and control, and earthquakes. The demand for high-precision, low-power analog-to-digital converters (ADCs) in electronic equipment such as medical, instrumentation, etc. is increasing day by day. The ADC converts real-world analog signals into digital signals. A complete digital information system must include ADCs and digital-to-anal...

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Problems solved by technology

The auxiliary ADC correction technology has high precision and is easy to integrate on-chip. However, in addition to the design of the main ADC, this correction method also needs to design another more accurate auxiliary ADC, which increases the complexity of the design and increases the power consumption and power consumption of the chip. area

Scheme 3: "Least mean square error" (LMS) algorithm digital correction method, the literature includes W.Liu, P.Huang, Y.Chiu, "A 12-bit, 45-MS / s, 3-mW Redundant Successive Approximation Register analog-to-Digital Converter With Digital Calibration," IEEE Journal of Solid-State Circuits, 2011, 46(11): 2661–2672; this method converts the same input voltage twice, and the LMS algorithm is based on the difference between the two conversion results of the ADC , to calculate the capacitance mismatch error and correct it. Although this algorithm does not require an accurate reference source, converting the same input voltage twice results in the sampling rate being reduced by half, which seriously sacrifices speed.

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