High-breakdown voltage field effect transistor and fabrication method thereof
A field-effect transistor and high breakdown voltage technology, which is applied in transistors, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problem of low withstand voltage and achieve the effect of simple preparation process and improved breakdown voltage
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example 1
[0039] Example 1, the production substrate is sapphire, Si ions are implanted, and the insulating gate dielectric is Si 3 N 4 high breakdown voltage field effect transistors.
[0040] Step 1: Wash the sample as Figure 4 (a) shown.
[0041] Ga 2 o 3 The sample was cleaned organically, washed with flowing deionized water, and then placed in HF:H 2 Corrosion in the solution of O=1:1 for 60s;
[0042] Then rinse with flowing deionized water and blow dry with high-purity nitrogen.
[0043] Step 2: Deposit SiO 2 mask, such as Figure 4 (b) shown.
[0044] Put the cleaned sample into the PECVD equipment, set the reaction chamber pressure to 2Pa, the RF power to 40W, and simultaneously feed SiH with a flow rate of 40sccm 4 and a flow rate of 10 sccm N 2 O, in n-type Ga 2 o 3 SiO with a thickness of 50 nm was deposited on the film 2 mask.
[0045] Step 3: Make the ion implantation area, such as Figure 4 (c) shown.
[0046] 3a) For complete SiO 2 The sample deposited...
example 2
[0063] Example 2, making the substrate as Ga 2 o 3 , implanted Sn ions, and the insulating gate dielectric is HfO 2 high breakdown voltage field effect transistors.
[0064] Step 1: Wash the sample, such as Figure 4 (a) shown.
[0065] This step is the same as Step 1 of Example 1.
[0066] Step 2: Deposit SiO 2 mask, such as Figure 4 (b) shown.
[0067] This step is the same as Step 2 of Example 1.
[0068] Step 3: Make the ion implantation area, such as Figure 4 (c) shown.
[0069] 3.1) To complete SiO 2 The sample deposited by the mask is subjected to photolithography to form an ion implantation region;
[0070] 3.2) Put the photolithographic sample into the ion implantation reaction chamber to perform Sn ion implantation twice, the first implantation energy is 60keV, and the implantation dose is 3.2×10 14 cm -2 ; The second implantation energy is 30keV, and the implantation dose is 9.3×10 13 cm -2 ;
[0071] 3.3) Put the sample implanted with Sn ions into...
example 3
[0086] Example 3, making the substrate as MgAl 2 o 4 , implanted Ge ions, and the insulating gate dielectric is Al 2 o 3 high breakdown voltage field effect transistors.
[0087] Step A: Wash the sample as Figure 4 (a) shown.
[0088] This step is the same as Step 1 of Example 1.
[0089] Step B: Deposit SiO 2 mask, such as Figure 4 (b) shown.
[0090] This step is the same as Step 2 of Example 1.
[0091] Step C: making the ion implantation area, such as Figure 4 (c) shown.
[0092] C1) to complete SiO 2 The sample deposited by the mask is subjected to photolithography to form an ion implantation area;
[0093] C2) Put the photoetched sample into the ion implantation reaction chamber to perform Ge ion implantation twice, the first implantation energy is 60keV, and the implantation dose is 3.2×10 14 cm -2 ; The second implantation energy is 30keV, and the implantation dose is 9.3×10 13 cm -2 ;
[0094] C3) Put the Ge ion-implanted sample into an annealing fur...
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