Semiconductor device, manufacturing method of the semiconductor device, and electronic device

Abstract

The invention relates to a semiconductor device, a manufacturing method of the semiconductor device, and an electronic device. The manufacturing method of the semiconductor device includes the steps: S1, providing a semiconductor substrate which includes a high voltage device region and a low voltage device region, and forming a patterned high voltage gate oxide layer on the high voltage device region; S2, forming a low voltage gate oxide layer at two sides of the low voltage device region and the high voltage gate oxide layer; S3, forming a low voltage gate structure and clearance walls of the low voltage gate structure on the low voltage gate oxide layer, and forming a high voltage gate structure and clearance walls of the high voltage gate structure at the same time, wherein the sum of key sizes of the clearance walls and the high voltage gate structure in the high voltage device region is equal to the key size of the high voltage gate oxide layer; S4, forming a metal silicide barrier layer in the high voltage device region and the low voltage device region and patterning the metal silicide barrier layer; S5, removing the exposed low voltage gate oxide layer; and S6, forming self-aligning silicides on the regions and the high voltage gate structure.

Description

technical field [0001] The present invention relates to the field of semiconductors, in particular, the present invention relates to a semiconductor device, a preparation method, and an electronic device. Background technique [0002] With the increasing demand for high-capacity semiconductor storage devices, the integration density of these semiconductor storage devices has received more attention. In order to increase the integration density of semiconductor storage devices, many different methods have been adopted in the prior art, such as through To reduce the size of the wafer and / or change the structural unit to form multiple memory cells on a single wafer, for the method of increasing the integration density by changing the unit structure, you can try to change the planar layout of the active region or change the cell layout. Reduce the cell area. [0003] In the micron-scale and sub-micron-scale integrated circuit manufacturing processes, two kinds of devices with s...

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Problems solved by technology

[0005] Since the dry etching process is mainly through the action of plasma (Plasma), the main function of dry etching combined with wet etching is to prevent dry etching from completely etching the oxide, and the introduced plasma (Plasma) will have a thin gate Oxide low voltage MOS (LVMOS) will affect and even cause device failure

However, in the conventional semiconductor manufacturing process, the product with photoresist on the surface is soaked and impacted by the acid solution in the wet acid tank, and the photoresist peeling off (PR Peeling) of the metal silicide barrier layer will be a common defect problem. This defect phenomenon will cause the disorder of the metal silicide area, affect the contact resistance of the device, and cause a series of problems such as low yield rate of the product; and the service life of the wet chemical solution is short, which is not conducive to the production cost

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