Horizontal structure-based LED and preparation method therefor
A lateral structure and process technology, applied in electrical components, circuits, semiconductor devices, etc., can solve the problems of preparation, large lattice mismatch, high dislocation density of Ge buffer layer, and achieve low dislocation density, which is conducive to integration, The effect of high luminous efficiency
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Embodiment 1
[0044] See figure 1 , figure 1 A flow chart of a fabrication method based on a lateral structure LED provided in an embodiment of the present invention, including:
[0045] (a) select SOI substrate;
[0046] (b) using a CVD process to grow a Ge seed layer, a Ge bulk layer and an oxide layer on the SOI substrate in sequence;
[0047] (c) using the LRC process to crystallize the Ge seed layer and the Ge host layer to form a crystallized Ge epitaxial layer;
[0048] (d) etching the oxide layer by a dry etching process;
[0049] (e) growing a GeSn layer on the surface of the crystallized Ge epitaxial layer;
[0050] (f) respectively implanting P ions and B ions into the Ge epitaxial layer to form an N-type Ge region and a P-type Ge region;
[0051] (g) Making metal contact electrodes to complete the preparation of the lateral structure LED.
[0052] Preferably, step (b) may include:
[0053] (b1) growing a Ge seed layer on the surface of the SOI substrate by using a CVD pro...
Embodiment 2
[0074] Please refer to Figure 2a-Figure 2l , Figure 2a-Figure 2l It is a schematic process flow diagram of another preparation method based on a lateral structure LED according to an embodiment of the present invention, and the preparation method includes the following steps:
[0075] S201. Substrate selection. Such as Figure 2a As shown, the SOI substrate 001 is selected as the initial material;
[0076] S202, Ge seed layer growth. Such as Figure 2b As shown, at a temperature of 275° C. to 325° C., a Ge seed layer 002 of 40 to 50 nm is epitaxially grown by a CVD process;
[0077] S203, Ge main body layer growth. Such as Figure 2c As shown, at a temperature of 500°C-600°C, a CVD process is used to grow a Ge main layer 003 with a thickness of 120-150nm on the surface of the Ge seed layer 002;
[0078] S204, preparation of an oxide layer. Such as Figure 2d As shown, 150nm SiO was deposited on the surface of Ge host layer 003 by CVD process 2 layer oxide layer 00...
Embodiment 3
[0086] Please refer to image 3 , image 3 It is a schematic structural diagram of an LED based on a lateral structure provided by an embodiment of the present invention. The LED employs the above as Figure 2a-Figure 2l prepared as indicated. Specifically, the LED includes: SOI substrate (301), Ge epitaxial layer (302), GeSn layer (303), N-type Ge region (304), P-type Ge region (305), SiO 2 a passivation layer (306) and a metal contact electrode (307);
[0087] Wherein, the Ge epitaxial layer (302) includes a Ge seed crystal layer and a Ge main body layer; the Ge seed crystal layer and the Ge main body layer are crystallized by an LRC process to form the Ge epitaxial layer (302).
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Abstract
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