A bonding structure manufacturing method and bonding structure for multi-layer bonding stacking

Abstract

The present invention particularly relates to a bonding structure manufacturing method and bonding structure for multilayer bonding stacking. The method includes: depositing a front bonding point at a predetermined position on the surface of the dielectric layer of the wafer, the wafer includes a first substrate and a dielectric layer, and the dielectric layer contains a plurality of metal connection points; leading out part of the metal connection points to form metal transfer points; Through-hole etching is performed at the metal transfer point to form multiple through-holes; conductive metal deposition is performed inside the through-hole to fill the through-hole; thinning and chemical-mechanical planarization are performed on the surface of the substrate away from the dielectric layer until exposed Conductive metal, using conductive metal as the back bonding point, forms a bonding structure for multi-layer bonding stacking with bonding points on the front and back. The bonding and stacking of multiple wafers or chips can be realized through the method of the present invention, which can effectively improve the freedom of circuit design of integrated circuit chips and the effective utilization area of ​​chips, and reduce the large resistance and bandwidth reduction caused by too long wiring And other issues.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a bonding structure manufacturing method and bonding structure for multilayer bonding stacking. Background technique [0002] As electronic products, especially portable products such as mobile phones become smaller and smaller, but at the same time must be able to provide more and more functions, so it is necessary to integrate multiple functional chips, electronic components such as semiconductor devices are a multi- Made of laminated structure. [0003] To electrically connect components in different layers, through-silicon via (TSV) technology can be used to provide electrical interconnection and provide mechanical support. In through-silicon via technology, holes are drilled in specific areas of each silicon wafer and filled with metal. Finally, each perforated silicon wafer is stacked and bonded together and cut into individual chips. This wil...

AI Technical Summary

Problems solved by technology

Finally, each perforated silicon wafer is stacked and bonded together and cut into individual chips. This will not only lose the effective area of ​​each chip, but also increase the resistance of the chip and reduce the bandwidth because the interconnection line is too long. And other problems, more importantly, the freedom of circuit design is severely limited due to the fact that the location of the interconnection vias can only be located in a specific area of ​​the silicon wafer.

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