Semiconductor device and forming method thereof

Abstract

The invention discloses a semiconductor device and a forming method thereof. The forming method comprises steps: a first conductive plug is formed inside an interlayer dielectric layer, wherein the first conductive plug is electrically connected with a source and drain doping area; before or after the first conductive plug is formed, a gate electrode layer with a first thickness is etched and removed, and a blocking layer is formed at the top part of the gate electrode layer after etching; an upper dielectric layer is formed on the interlayer dielectric layer and the blocking layer; a second conductive plug passing through the upper dielectric layer is formed in the upper dielectric layer; and annealing treatment is carried out, the annealing treatment is carried out in an atmosphere containing passivated ions, the passivated ions are diffused to the base below the gate structure through the second conductive plug and the first conductive plug, and the passivated ions located in the base are diffused to a gate dielectric layer. While the interface performance between the gate structure and the base is improved, the passivated ions can be prevented from being diffused inside the gate electrode layer, and the electrical performance of the formed semiconductor device is thus improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a forming method thereof. Background technique [0002] The main semiconductor device of an integrated circuit, especially a very large scale integrated circuit, is a metal-oxide-semiconductor field effect transistor (MOS transistor). With the continuous development of integrated circuit manufacturing technology, the technology nodes of semiconductor devices are continuously reduced, and the geometric dimensions of semiconductor structures are continuously reduced following Moore's law. When the size of the semiconductor structure is reduced to a certain extent, various secondary effects caused by the physical limit of the semiconductor structure appear one after another, and it becomes more and more difficult to scale down the feature size of the semiconductor structure. Among them, in the field of semiconductor manufacturing, the most challeng...

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Problems solved by technology

[0004] Although the introduction of a high-k metal gate can improve the electrical performance of the device to a certain extent, the electrical performance of the device formed by the prior art still needs to be improved.

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