MOS (metal oxide semiconductor) capacitor with high K/ZnO content and low In ingredient InGaAs content and fabrication method

A capacitor and oxide layer technology, applied in the field of microelectronics, can solve problems such as hindering the development of InGaAs devices, capacitance dispersion in the accumulation area, and increased hysteresis voltage, so as to improve the Fermi level pinning effect, reduce power consumption, Effect of Reducing Gate Leakage

Inactive Publication Date: 2018-09-04
XIDIAN UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] Now, the higher interface defect density between high K / InGaAs has become an important factor affecting its electrical properties. The defect state density causes the Fermi level pinning, the hysteresis voltage increases, and the capacitance dispersion of the accumulation region hinders the InGaAs The development of devices, so finding ways to improve the high K / InGaAs interface state has become an important issue

Method used

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  • MOS (metal oxide semiconductor) capacitor with high K/ZnO content and low In ingredient InGaAs content and fabrication method
  • MOS (metal oxide semiconductor) capacitor with high K/ZnO content and low In ingredient InGaAs content and fabrication method

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Experimental program
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Effect test

Embodiment 1

[0032] Embodiment 1, making high K oxide is Al 2 o 3 , the channel layer is In with a thickness of 15nm 0.2 Ga 0.8 As, the substrate is a GaAs MOS capacitor.

[0033] In step 1, pretreatment is performed on the epitaxial material including the P-type substrate, the P-type GaAs buffer layer and the P-type InGaAs channel layer, as shown in 2(a).

[0034] 1.1) Degrease the epitaxial material sample in acetone and isopropanol, and then rinse it with deionized water;

[0035] 1.2) Soak the rinsed sample in a 1% HF solution for 60 seconds to remove the intrinsic oxide on the surface, then soak it in ammonium sulfide solution for 20 minutes, rinse it with deionized water after taking it out, and put it under N 2 Dry in atmosphere.

[0036] Step 2, depositing a ZnO passivation layer, such as figure 2 (b).

[0037] The pretreated epitaxial material sample was deposited 1nm thick ZnO by atomic layer deposition ALD process, and the deposition process parameters were: the precurso...

Embodiment 2

[0048] Embodiment 2, making high K oxide is ZrO 2 , the channel layer is 30nm thick In 0.2 Ga 0.8 As, the substrate is a MOS capacitor of InP.

[0049] In step 1, pretreatment is performed on the epitaxial material including the P-type substrate, the P-type GaAs buffer layer and the P-type InGaAs channel layer.

[0050] The specific realization of this step is the same as step 1 of embodiment 1

[0051] Step 2, using the atomic layer deposition ALD process, that is, the precursors are DEZn and H 2 O, a 3nm thick ZnO passivation layer was deposited on the pretreated epitaxial material sample at a temperature of 200°C.

[0052] Step 3, using the atomic layer deposition ALD process, that is, the precursors are zirconium tetradimethylamide and H 2 O, the temperature is 200°C. Under the condition of ZnO passivation layer deposited 5nm thick ZrO 2 oxide layer.

[0053] Step 4, will deposit ZrO 2 The sample after the oxidation layer was placed in an annealing furnace with a te...

Embodiment 3

[0057] Embodiment 3, making high K oxide is Al 2 o 3 , the channel layer is 20nm thick In 0.3 Ga 0.7 As, the substrate is a GaSb MOS capacitor.

[0058] In step A, the epitaxial material including the P-type substrate, the P-type GaAs buffer layer and the P-type InGaAs channel layer is pretreated.

[0059] The specific realization of this step is the same as step 1 of embodiment 1

[0060] Step B, depositing a ZnO passivation layer.

[0061] The pretreated epitaxial material sample, the precursor is DEZn and H 2 O, a 5nm thick ZnO passivation layer was deposited under the process conditions of 200°C.

[0062] Step C, depositing Al 2 o 3 oxide layer.

[0063] On the upper surface of the ZnO passivation layer, the atomic layer deposition ALD process is adopted, that is, the precursors are TMA and H 2 O, deposited 5nm thick Al at 200°C 2 o 3 oxide layer.

[0064] Step D, post-deposition annealing.

[0065] will deposit Al 2 o 3 The sample after the oxidation layer...

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Abstract

The invention discloses an MOS (metal oxide semiconductor) capacitor with a high K/ZnO content and a low In ingredient InGaAs content, and a fabrication method. The MOS capacitor mainly solves the problem of high density of an interfacial state of the existing similar device, and comprises an ohmic contact metal (1), a substrate (2), a GaAs buffer layer (3), an InGaAs channel layer (4), a ZnO passivation layer (5), a high K oxidation layer (6) and a metal gate electrode (7) from the bottom up. A doping concentration and thickness of the InGaAs channel layer are 1*10<17>/cm<3> and 15-30nm respectively; the thickness of the ZnO passivation layer is 1-5nm; and the high K oxidation layer adopts Al2O3 or ZrO2 and is 5-10nm in thickness. The density of the interfacial state of the device is reduced; a high K/InGaAs interface defect is improved; the breakdown field strength is improved; the electric leakage of the gate electrode is reduced; and the capacitor can be used for fabrication of a complementary metal oxide semiconductor device.

Description

technical field [0001] The invention belongs to the technical field of microelectronics, and specifically relates to a method for manufacturing MOS capacitors, which can be used for manufacturing complementary metal oxide semiconductor devices. Background technique [0002] In the past forty years, silicon-based complementary metal-oxide-semiconductor CMOS technology has followed Moore's Law, and has achieved great success by reducing the feature size and gate oxide thickness to improve performance, but the feature size of transistors has been reduced to 22nm. , Silicon-based CMOS technology faces both physical and technical challenges to improve performance by further reducing the size. With the reduction of size, power consumption has become the main technical problem to be faced by the semiconductor industry. [0003] In order to solve the power consumption problem of CMOS devices, the scientific research community and the industry have replaced Si with channel materials ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/94
CPCH01L29/94
Inventor 刘琛吕红亮杨彤张玉明张义门
Owner XIDIAN UNIV
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