Method for manufacturing composite gate IGBT (Insulated Gate Bipolar Transistor) chip with three-dimensional channel
A manufacturing method and compound gate technology, which are applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problem of not improving the current density and withstand voltage capability of the chip, and achieve the goal of improving the current density of the chip, increasing the channel density, Effect of increasing gate oxide thickness
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Embodiment 1
[0043] In order to solve the above-mentioned technical problems existing in the prior art, an embodiment of the present invention provides a method for manufacturing a composite gate IGBT chip with a three-dimensional channel.
[0044] figure 1 A schematic flow diagram showing a method for fabricating the upper surface structure of a composite gate IGBT chip with a three-dimensional channel in Embodiment 1 of the present invention; image 3 It shows a schematic diagram of the manufacturing method of the composite gate IGBT chip with a three-dimensional channel in Embodiment 1 of the present invention.
[0045] refer to figure 1 with image 3 In this embodiment, the method for fabricating a composite gate IGBT chip with a three-dimensional channel includes the following steps.
[0046] Step S101 , forming a first oxide layer 1 on the upper surface of the wafer substrate 2 .
[0047] Preferably, the wafer substrate 2 may be a silicon wafer, and the first oxide layer 1 is sil...
Embodiment 2
[0083] In order to solve the above-mentioned technical problems existing in the prior art, the embodiment of the present invention also provides another method for manufacturing a composite gate IGBT chip with a three-dimensional channel.
[0084] Figure 5 A schematic structural diagram of a compound gate IGBT chip with a three-dimensional channel manufactured by the method for manufacturing a compound gate IGBT chip with a three-dimensional channel in Embodiment 2 of the present invention is shown.
[0085] The embodiment method adds step 1021 between step S102 and step S103 on the basis of embodiment one, specifically as follows:
[0086] Step 1021 , implanting N-type impurities into the second predetermined position of the exposed wafer substrate 2 , and diffusing them to a third junction depth to form an N well 15 , the third junction depth being greater than the first junction depth.
[0087] At this point, step 103 should be: implanting P-type impurities into the N wel...
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