double-link interconnection architecture based on a three-dimensional Mesh network-on-chip

Abstract

The network-on-chip effectively transplants the related technologies of the macrocomputer and the parallel computing network into the chip design through the design of separating the computing from the communication, has the advantages of good expansibility, high communication efficiency, low transmission energy consumption, high reliability and the like, and completely solves the problems causedby the traditional bus architecture from the architecture of the system. The invention discloses a double-link interconnection architecture based on a three-dimensional Mesh network-on-chip in order to meet the requirement of future multi-core network-on-chip development. In the vertical direction, the architecture adopts double-link interconnection, so that the communication bandwidth of the architecture is doubled; Moreover, different layers are connected by adopting a vertical link, so that the routing hop count of message transmission is reduced. By adding a small number of control logic circuits, the average delay of the network can be reduced, and the maximum throughput of the network can be improved. And a simulation result verifies theoretical analysis. Compared with a traditionalsingle link architecture, the architecture has the advantage that the performance is greatly improved with small area overhead.

Description

Technical field [0001] The invention relates to the design of network architecture on chip, in particular to the design of chip architecture with multi-processor cores and high communication density in the future. Background technique [0002] With the increase in the types of electronic product applications, whether it is in the field of high-performance computing, or core network equipment, base stations, and personal mobile communication terminals, higher requirements are placed on the performance of processors. In the past, the method of improving processor performance by increasing the main frequency of the chip has faced a physical bottleneck, and multi-core technology has gradually become an inevitable trend in the development of high-performance chips. Therefore, it is becoming more and more important to provide an efficient interconnection and communication system for many processor cores of a large-scale system-on-chip. Existing bus-based on-chip interconnect stru...

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Problems solved by technology

[0003] At present, there are many studies on two-dimensional network on chip, but with the increasing computational complexity of communication terminals and equipment in the future, the scale of IC will become larger and larger. However, due to the limitation of two-dimensional network on chip layout conditions, in some In this case, the critical path is long, and the corresponding energy consumption, signal delay and crosstalk are relatively large, which constrains the topology optimization and performance improvement of the network on chip

Therefore, as the number of IP cores increases, the communication performance of the two-dimensional network-on-chip cannot be improved proportionally as expected.

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