JCD integrated device based on N-type epitaxy and preparation method thereof

Abstract

The invention provides a JCD integrated device based on N-type epitaxy and a preparation method thereof, and belongs to the technical field of power semiconductor integration. The high-simulation precision JFET part, the CMOS part with high integration degree, convenient logic control and low power consumption and the high-voltage control DMOS part with the high switching speed are integrated on the same chip for the first time, so that the chip has the system function. At the same time, passive components such as poly capacitors, poly resistors and poly diodes can be integrated with the chipto form a circuit. Such a rich device type can bring great flexibility to the power circuit design. The overall process uses fewer masks, the process level reusability is strong, and the manufacturingcost control can be facilitated. High and low voltage compatibility, high performance, high efficiency and high reliability are achieved on the limited chip area. The chip made by using the JCD integration technology has better comprehensive performance and is favorable for development of the one-chip power system integration.

Description

technical field [0001] The invention belongs to the technical field of power semiconductor integration, and in particular relates to an N-type epitaxy-based JCD integrated device and a preparation method thereof. Background technique [0002] For more than 40 years, semiconductor technology has continuously reduced the chip feature size along the route of Moore's Law. However, semiconductor technology has developed to a bottleneck: as the line width becomes smaller and smaller, the manufacturing cost increases exponentially; and as the line width approaches At the nanometer scale, the quantum effect is becoming more and more obvious, and the leakage current of the chip is also increasing. Therefore, the development of semiconductor technology must consider the "post-Moore era" issue. In 2005, the international technology roadmap for semiconductors (ITRS for short) proposed the concept of more than Moore. Power semiconductor devices and power integration technology play a v...

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Problems solved by technology

[0002]For more than 40 years, semiconductor technology has been shrinking the chip feature size along the route of Moore's Law. However, semiconductor technology has developed to a bottleneck: with the increasing line width The smaller the size, the manufacturing cost increases exponentially; and as the line width approaches the nanometer scale, the quantum effect becomes more and more obvious, and the leakage current of the chip becomes larger and larger

However, the integration technology of JFET devices still has many problems such as compatibility and poor performance of JFET devices.

Due to the particularity of the double-gate structure of the JFET device itself, there are still integration issues for the technical personnel to realize the monolithic integration of the low-voltage JFET, the high-voltage control part, and the low-voltage logic part, the compatibility of the high-voltage DMOS and the low-voltage JFET part, and the compatibility of the JFET and CMOS parts. Obstacles, due to the complex manufacturing process of JFET devices, its saturation characteristics and pinch-off characteristics are difficult to meet the application requirements at the same time, resulting in restrictions on the performance of JFET devices and the development of related integrated op amps

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