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Chip stack stereoscopic package structure and manufacturing method thereof

A technology of three-dimensional packaging and chip stacking, which is applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve the problems that affect the overall yield rate of the stacked packaging structure, low wafer yield rate, cost loss, etc., and achieve improvement The effects of signal quality, improved bonding efficiency, and reduced production costs

Active Publication Date: 2019-05-24
CHANGXIN MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] On the other hand, the existing wafer-to-wafer connection method is to test the wafers after the wafer bonding and stacking are completed. At this time, if the yield rate of a certain wafer is found to be too low, it will affect the stack packaging The overall yield of the structure, resulting in a loss of cost

Method used

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  • Chip stack stereoscopic package structure and manufacturing method thereof
  • Chip stack stereoscopic package structure and manufacturing method thereof
  • Chip stack stereoscopic package structure and manufacturing method thereof

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Embodiment approach 1

[0109] figure 2 It is a schematic diagram of the chip stack three-dimensional package structure provided by an embodiment of the present invention. Such as figure 2 As shown, the three-dimensional chip stack package structure 200 according to the embodiment of the present invention includes: a chip stack body 210, a first redistribution layer 220, flip-chip terminals 230, a substrate 240, a primer 250, a plastic package body 260, and a second metal pad 270 , External terminal 280. Wherein, the chip stack 210 includes: a top chip 211, a second chip 212, a first chip 213 and a bottom chip 214; the top chip 211 has a top active surface 211A and a crystal back 211B opposite to the top active surface 211A; The first chip 213 has a first active surface 213A and a stack back surface 213B opposite to the first active surface 213A, and the bottom chip 214 has a mounting surface 214A and The stack back 214B opposite to the mounting surface 214A; the active surface of each chip and ...

Embodiment approach 2

[0130] figure 2 In the chip stack three-dimensional packaging structure shown, the bottom chip 214 can be a different chip from the top chip 211, the second chip 212 and the first chip 213, such as Figure 4 shown. In some embodiments, the top chip 211 , the second chip 212 and the first chip 213 are memory chips, such as DRAM (Dynamic Random Access Memory, Dynamic Random Access Memory) chips, and the bottom chip 214 is a buffer chip. The buffer chip is to separate the circuit used to control data transmission in the memory chip and set it as an independent control chip, and it is made by using a process different from that of the memory chip. Its response speed is much higher than that of the memory chip to improve data transmission. transfer speed.

[0131] It should be noted that although the bottom chip 214 is different from the top chip 211 , the second chip 212 and the first chip 213 , the structure of the bottom chip 214 is the same as that of the second chip 212 and...

Embodiment approach 3、4

[0133] figure 2 and Figure 4 The chip stack three-dimensional packaging structure shown can also only stack three layers of chips, and the specific structures are as follows: Figure 5 and Figure 6 shown. Figure 5 implementation of Figure 6 The implementation of the differs in that Figure 5 The bottom chip 214 in is the same chip as the top chip 211 and the first chip 213, while Figure 6 The bottom chip 314 in is a different chip from the top chip 211 and the first chip 213 Figure 5 and Figure 6 respectively with figure 2 and Figure 4 Descriptions of the same parts shown can be found in the figure 2 and Figure 4 description and will not be repeated here.

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Abstract

The invention provides a chip stack stereoscopic package structure and a manufacturing method thereof. The package structure includes a chip stack which includes a first chip and a bottom chip directly joined in a gap-free manner. The first chip has first test pads and first perforations, and the bottom chip has bottom test pads and bottom perforations. A first landing pad and a bottom landing padare formed at one end of each first perforation and at one end of each bottom perforation respectively. The bottom perforations penetrate the bottom test pads and are communicated to the first landing pads, so as to make the bottom chip and the first chip electrically connected. The manufacturing method includes the following steps: forming test pads on the surfaces of wafers and testing the wafers with the test pads, and directly joining the wafers meeting the yield reference value; forming perforations and landing pads to form electrical connections between the wafers; and carrying out monolithic cutting to form a chip stack stereoscopic package structure. Through direct wafer joining, the signal transmission distance between chips is shortened, and the package size is reduced. The yield is tested before wafer joining, so that low-yield wafers are prevented from being stacked, and cost is saved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a chip stack three-dimensional packaging structure and a manufacturing method thereof. Background technique [0002] With the development of electronic products in the direction of miniaturization, high density and high performance, based on through silicon vias [0003] (Through Silicon Via, TSV) 2.5D (2.5Dimensional, 2.5-dimensional) and 3D (Threedimensional, 3-dimensional) stack packaging has increasingly become the dominant technology in the field of high-density packaging. At present, for chips with TSVs, micro-bumps are usually generated on the surface of the chip, and chip-to-chip (C2C) or chip-to-wafer (C2W) is connected by reflow soldering. And form a chip stack structure. figure 1 It is a typical stack package structure of memory die and buffer die. As shown in the figure, memory chips 112, 113 and buffer chip 114 have through-silicon vias 112C, 1...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/538H01L23/544H01L21/768
Inventor 不公告发明人
Owner CHANGXIN MEMORY TECH INC
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