Amorphous silicon thin film transistor

A technology of transistors and amorphous silicon thin films, applied in the field of thin film transistors, can solve the problem of small signal-to-noise ratio of sensors, and achieve the effects of improving signal-to-noise ratio, reducing noise, and reducing ratio

Pending Publication Date: 2019-06-25
上海易密值半导体技术有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0009] The purpose of the present invention is to overcome the deficiencies of the prior art, provide an amorphous silicon thin film transistor and its prep

Method used

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Example Embodiment

[0052] The present invention also provides a method for manufacturing the above-mentioned thin film transistor, which includes the following steps:

[0053] Along the direction extending from the inner surface of the substrate to the surface, a substrate 1, a gate 2, a gate insulating layer 3 and an amorphous silicon semiconductor layer 4 are sequentially formed on the surface of the substrate;

[0054] A conduction band energy layer 5 is respectively formed on one end or both end surfaces of the amorphous silicon semiconductor layer, and;

[0055] An ohmic contact layer 7 is respectively formed on the conduction band energy layer 5 coupled to both ends of the amorphous silicon semiconductor layer 4; or on the conduction band distributed at one end of the amorphous silicon semiconductor layer 4 An ohmic contact layer 7 is formed on the energy layer 5, and an ohmic contact layer 7 is directly formed on the other end of the amorphous silicon semiconductor layer 4;

[0056] A source elec...

Example Embodiment

[0063] Example 1

[0064] The amorphous silicon thin film transistor of one embodiment of the present invention is such as figure 1 Shown includes: a glass substrate 1; a grid 2, combined on a surface of the substrate 1; a grid insulating layer 3, combined on the surface of the substrate and covering the grid 2; a semiconductor layer, combined with the grid insulating layer The surface away from the substrate; the semiconductor layer includes an amorphous silicon semiconductor layer 4; the amorphous silicon semiconductor layer 4 is bonded to the gate insulating layer 3 on the surface away from the gate 2; the ohmic contact layer 7, including each other The two parts of the gap are respectively combined on the two ends of the surface of the amorphous silicon semiconductor layer away from the gate insulating layer; the source electrode and the drain electrode are respectively combined on the ohmic contact layer 7; and the passivation layer 8. The semiconductor layer further include...

Example Embodiment

[0071] Example 2

[0072] The amorphous silicon thin film transistor of one embodiment of the present invention is such as figure 1 Shown includes: a glass substrate 1; a grid 2, combined on a surface of the substrate 1; a grid insulating layer 3, combined on the surface of the substrate and covering the grid 2; a semiconductor layer, combined with the grid insulating layer The surface away from the substrate; the semiconductor layer includes an amorphous silicon semiconductor layer 4; the amorphous silicon semiconductor layer 4 is bonded to the gate insulating layer 3 on the surface away from the gate 2; the ohmic contact layer 7, including each other The two parts of the space are respectively combined on the two ends of the surface of the amorphous silicon semiconductor layer away from the gate insulating layer; the source electrode and the drain electrode are respectively combined on the ohmic contact layer 7; and the passivation layer 8. The semiconductor layer further inclu...

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Abstract

The invention provides an amorphous silicon thin film transistor and a preparation method thereof. The amorphous silicon thin film transistor comprises a gate formed on a glass substrate, a gate insulating layer, an amorphous silicon semiconductor layer formed on the outer surface of the gate insulating layer, and a source and a drain formed on the semiconductor layer, wherein a passivation layerwrapping the semiconductor layer, the source and the drain is disposed on the gate insulating layer. The amorphous silicon thin film transistor is characterized by further comprising semiconductor materials having energy similar to the energy of an amorphous silicon valence band but having higher conduction band energy, wherein the semiconductor materials are spaced apart at both ends of the semiconductor layer. The amorphous silicon thin film transistor is mainly applied to a sensor, especially directly applied to a photosensitive sensor. The high energy level difference reduces the transition ratio of the electrons that generate noise signals, and increases a signal-to-noise ratio.

Description

technical field [0001] The invention belongs to the field of semiconductors, and in particular relates to a thin film transistor. Background technique [0002] TFT is to deposit a thin film on the substrate (if it is used in liquid crystal display, the substrate is mostly glass) as the channel area. [0003] Most TFTs use hydrogenated amorphous silicon (a-Si:H) as the main material, because its energy level is smaller than that of single crystal silicon (Eg=1.12eV), and because a-Si:H is used as the main material, So TFTs are mostly not transparent. In addition, TFT often uses indium tin oxide (ITO) in the dielectric, electrodes and internal wiring, and ITO is a transparent material. [0004] Because TFT substrates cannot tolerate high annealing temperatures, all deposition processes must be performed at relatively low temperatures. For example, chemical vapor deposition and physical vapor deposition (mostly using sputtering technology) are commonly used deposition proces...

Claims

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Application Information

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IPC IPC(8): H01L29/06H01L21/336H01L29/786
Inventor 张源
Owner 上海易密值半导体技术有限公司
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