Silicon-based charge trapping memory device and preparation method
A technology of charge trapping and storage devices, which is applied in the fields of electrical solid-state devices, semiconductor/solid-state device manufacturing, electrical components, etc. It can solve the problems of poor retention performance, achieve good retention performance and improve storage performance.
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Embodiment 1
[0019] The structure of the non-volatile charge-trapping memory device includes a substrate, a tunneling layer, a charge-trapping dielectric layer, a blocking layer and a gate electrode;
[0020] The tunneling layer is an insulating layer with a thickness of 1-5nm. The preparation methods include physical deposition methods, such as radio frequency magnetron sputtering methods and electron beam evaporation methods, etc., and can also be prepared by chemical deposition methods, such as atomic layer deposition methods (ALD method );
[0021] The charge trapping dielectric layer is an insulating layer with a thickness of 0.5-20nm. The preparation methods include physical deposition methods, such as radio frequency magnetron sputtering methods and electron beam evaporation methods, etc., and can also be prepared by chemical deposition methods, such as atomic layer deposition methods (ALD methods);
[0022] The barrier layer is an insulating layer with a thickness of 5-20nm. The p...
specific Embodiment 2
[0041] The difference between this embodiment and Embodiment 1 is that the tunneling layer is an insulating layer with a thickness of 1-5 nm. 2 , is prepared by thermal oxidation method.
[0042] In the SiO 2 layer is another layer of Al 2 o 3 , using the atomic layer deposition technique (ALD method), at 200 ° C on the above SiO 2 Al 2 o 3 tunneling layer;
[0043] SiO 2 Al 2 o 3 The total thickness of the layers is 1-5 nm.
[0044] on p-Si substrate and Al 2 o 3 A layer of thermally oxidized SiO is added between 2 is to reduce p-Si substrate and Al 2 o 3 The interfacial state density improves the retention performance of memory devices.
[0045] by Figure 5 As an example, give an example of a specific implementation method. Figure 5 Among them, 1 is the p-Si substrate with crystal orientation, and the resistivity is 1~10Ω / cm; 2-1 is SiO 2 Tunneling layer with a thickness of 1nm; 2-2 is Al 2 o 3 The tunneling layer has a thickness of 2nm; 3 is (Al 2 o ...
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