Polarization-doped inn-based tunneling field-effect transistor and manufacturing method thereof

Abstract

The invention discloses a polarization-doped InN-based tunneling field effect transistor, and the problem that the random doping fluctuation caused by the conventional physical doping technology leadsto a decrease in device performance, the manufacturing process is complicated and the reliability is low are mainly solved. The polarization-doped InN-based tunneling field effect transistor comprises a substrate (1), a buffer layer (2) and a body region (3) from the bottom to top. An upper right part of the body region is provided with a polarized inversion layer (4), a dielectric layer (8) is deposited on an upper portion of the body region and a left side and an upper portion of the polarized inversion layer, a gate step (9) is etched on the left side of the dielectric layer, a modulationplate (10), a gate electrode (11) and a tunneling gate (12) are orderly deposited on an upper part of the dielectric layer from the right to the left, lower steps (5) are etched at two sides of the body region, and the upper parts of the left and right sides of the steps are provided with a source electrode (7) and a drain electrode (6). According to the invention, the annealing process in the traditional physical doping technology is avoided, the output current and sub-threshold swing of a device are improved, the device reliability is improved, and the polarization-doped InN-based tunnelingfield effect transistor can be used in a low-power circuit system.

Description

technical field [0001] The invention belongs to the technical field of semiconductor devices, and in particular relates to a tunneling field effect transistor which can be used in a low power consumption circuit system. [0002] technical background [0003] With the advancement of technology, the ever-increasing silicon chip area and the shrinking transistor feature size have led to the rapid development of VLSI technology, which has led to the gradual reduction of the manufacturing cost of a single transistor and the continuous improvement of the electrical characteristics of the entire chip. At present, CMOS process technology has entered the 14nm era, and it is still shrinking, advancing towards 7nm and below technology nodes. Today, billions of devices can be integrated on a single chip. However, as the size of transistors shrinks to the nanometer level, problems such as short channel effects become more and more serious, especially the sharp increase in power consumptio...

AI Technical Summary

Problems solved by technology

Devices with this structure, due to the use of traditional physical doping technology, will encounter the same problems as traditional physically doped silicon-based tunneling field effect transistors, such as the inherent high cost of the ion implantation process and its accompanying expensive annealing technology , as well as random doping fluctuation RDFs, the performance of the device is reduced, the complexity of the process is increased, and the reliability of the device is reduced.

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