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All-covalent bond graphene field effect transistor and construction method thereof

A field-effect transistor and graphene technology, which is applied in the manufacture of transistors, semiconductor devices, semiconductor/solid-state devices, etc., can solve problems such as low electron mobility and Dirac point shift, so as to improve electrical performance and reduce injection potential Barrier, improve the effect of solvent stability and electrical stability

Active Publication Date: 2020-09-22
UNIV OF JINAN
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the electron mobility of the device is not high, and the Dirac point in the bipolar transmission characteristic curve shifts

Method used

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  • All-covalent bond graphene field effect transistor and construction method thereof
  • All-covalent bond graphene field effect transistor and construction method thereof
  • All-covalent bond graphene field effect transistor and construction method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0040] (1) Immerse the substrate in piranha solution (concentrated sulfuric acid:hydrogen peroxide = 7:3) at 100°C for 8 minutes, rinse it with deionized water three times, and ultrasonically clean it for 10 minutes. Then, the substrate was treated for 10 minutes with plasma and rf power of 100 W under the environment of an oxygen flow of 20 sccm.

[0041] (2) The method of preparing APTMS / GO monolayer on the substrate obtained in step (1) is repeated once to prepare TPPNH 2 / GO monolayer approach 4 times to form (APTMS / GO) / (TPPNH 2 / GO) layer.

[0042] (3) The load obtained in step (2) (APTMS / GO) / (TPPNH 2 A mask plate (channel length: 25 μm, channel width: 205 μm) is pasted on the substrate of the layer, and then an aluminum film with a thickness of 50 nm is evaporated, and the mask plate is removed after evaporation, and then passed through Under the environment of 20sccm oxygen gas flow, when the rf power is 100W with plasma, the substrate is treated for 10min, and the (...

Embodiment 2

[0046] (1) Immerse the substrate in piranha solution (concentrated sulfuric acid:hydrogen peroxide = 7:3) at 100°C for 8 minutes, rinse it with deionized water three times, and ultrasonically clean it for 10 minutes. Then, the substrate was treated for 10 minutes with plasma and rf power of 100 W under the environment of an oxygen flow of 20 sccm.

[0047] (2) The method for preparing the APTMS / GO monolayer on the substrate obtained in step (1) is repeated once, and the method for preparing the TPPNH2 / GO monolayer is repeated 4 times to form (APTMS / GO) / (TPPNH 2 / GO) layer.

[0048] (3) The load obtained in step (2) (APTMS / GO) / (TPPNH 2 A mask plate (channel length: 25 μm, channel width: 205 μm) is pasted on the substrate of the layer, and then an aluminum film with a thickness of 50 nm is evaporated, and the mask plate is removed after evaporation, and then passed through Under the environment of 20sccm oxygen gas flow, when the rf power is 200W with plasma, the substrate is ...

Embodiment 3

[0052] (1) Immerse the substrate in piranha solution (concentrated sulfuric acid:hydrogen peroxide = 7:3) at 100°C for 8 minutes, rinse it with deionized water three times, and ultrasonically clean it for 10 minutes. Then, the substrate was treated for 10 minutes with plasma and rf power of 100 W under the environment of an oxygen flow of 20 sccm.

[0053] (2) The method for preparing the APTMS / GO monolayer on the substrate obtained in step (1) is repeated once, and the method for preparing the TPPNH2 / GO monolayer is repeated 4 times to form (APTMS / GO) / (TPPNH 2 / GO) layer.

[0054] (3) The load obtained in step (2) (APTMS / GO) / (TPPNH 2 A mask plate (channel length: 25 μm, channel width: 205 μm) is pasted on the substrate of the layer, and then an aluminum film with a thickness of 50 nm is evaporated, and the mask plate is removed after evaporation, and then passed through Under the environment of 20sccm oxygen gas flow, when the rf power is 200W with plasma, the substrate is ...

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Abstract

The invention discloses anall-covalent bond graphene field effect transistor and a construction method thereof. The method comprises the following steps: processing a substrate, loading an APTMS / GO layer and a TPPNH2 / GO layer on the substrate, carrying out mask etching on the substrate to form an array, loading an APTMS / GO layer, and carrying out one-step annealing to obtain the all-covalent bondgraphene field effect transistor. According to the invention, anelectrode of the all-covalent bond graphene field effect transistor is connected with asemiconductor through a stable chemical bond, thereby greatly reducing the injection barrier of charges between the electrode and the semiconductor, and greatly improving the solvent stability and electrical stability of a device. A large pi systemcompound TPPNH2 with a large number of delocalized electron clouds on the surface is used as a coupling agent, and a good carrier injection and transmission channel is constructed along the molecularskeleton of the compound, so that the electrical property of the all-covalent bond graphene field effect transistor is improved.

Description

technical field [0001] The invention relates to the technical field of field effect transistors, in particular to an all-covalent bond graphene field effect transistor and a construction method thereof. Background technique [0002] Field-effect transistors (FETs) are one of the core components of many electronic devices such as integrated circuits, active matrix displays, electronic paper, light-emitting field-effect transistors, and sensors. However, most FET devices are connected by van der Waals force, and their physical structure is easily damaged during post-production processing, especially in solution processing, thereby reducing the stability of electrical signal output and causing a decline in device performance. In addition, since FET is a typical three-terminal electronic device, in order to achieve high performance and high integration of the device, various microelectromechanical systems (MEMS) technologies such as vapor deposition, thermal evaporation depositi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/04H01L29/786
CPCH01L21/0405H01L21/043H01L29/66045H01L29/78618H01L29/78684Y02P70/50
Inventor 张丛丛刘宏孙铭远王建
Owner UNIV OF JINAN
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