[0108]Third embodiment
[0109]Figure 5 Schematic diagram of trench type silicon carbide MOSFET for integrated SBD. Such asFigure 5 The first conductivity type substrate 2, the first conductivity type drift region 3, the Schott Fire 4, the polysilicon gate 5, the gate insulating layer 6, the second conductivity type well region 7, the first conductivity type Source region 8, second conductivity type enhancement zone 9, source metal 10, drain metal 11, source block metal 12, interlayer medium 13.
[0110]The first conductive type substrate 2 in this specification may include various semiconductor elements, such as silicon or silicon germanium of single crystal, polycrystalline or amorphous structure, or mixed semiconductor structure, such as silicon carbide, gallium gallium nitride, Indium phosphide, gallium arsenide, alloy semiconductor, or a combination thereof, is not limited herein. In the first conductive type substrate 2 in this embodiment, the silicon carbide substrate can be employed, and an n-type or p-type silicon carbide substrate can be used as an example in this example.
[0111]In this embodiment, the first conductivity type is an n-type, and the second conductivity type is a p-type.
[0112]This embodiment provides a cell structure of a silicon carbide MOSFET device, including:
[0113]The first conductivity type drift region 3 located on the first conductive type substrate layer 2;
[0114]The main trench 4 provided downward in the surface of the first conductivity type drift region 3, the bottom of the main groove and the Schottt Fire 4 are provided on the surface of the side wall surface;
[0115]The second conductive type well region 7 is located in the surface of the first conductivity type drift region 3 and the periphery of the main trench is set;
[0116]The first conductivity type source region 8 located in the surface of the second conductivity type well region 7, wherein the source region is located on one side of the second conductivity type well region 7 but is not in contact with the main trench;
[0117]The gate structure located on one side of the first conductivity type source region 8, the second conductivity type well region 7, and the first conductivity type drift region 3, wherein the gate structure includes a polysilicon gate 5 and a polysilicon. The gate 5 and the first conductive type source region 8, the second conductive type well region 7, and the gate insulating layer 6 isolated from the first conductive type drift region 3;
[0118]The source metal 10 located on the first conductivity type source region 8; and a drain metal 11 located below the first conductive type substrate 3;
[0119]Among them, the source metal 10 is connected to the Schott Fire 4 by the source pressure block metal 12 above, and the polysilicon gate 5 is isolated from the source metal 10, the Schott Fire 4 and the source block metal 12 in the gate structure.
[0120]In this embodiment, in addition to the first conductivity type source region 8, the second conductive type well region 7 further includes a second conductive type enhancement zone 9, wherein the second conductivity type enhancement region 9 is located at the second conductivity type well region 7. Keep away from the side of the main trench;
[0121]The source metal 10 is simultaneously located on the first conductivity type source region 8 and the second conductivity type enhancement region 9.
[0122]In the present embodiment, the shape of the trench in which the Schottt Fire 4 is in the shape of a rectangle, the like, semicircular, semi-elliptical, or other symmetrical structure.
[0123]Specifically, the MOSFET device of the present invention includes a higher concentration of first conductive type substrate 2, a concentration of greater than 1 × 1018cm-3. A first conductivity type drift region 3 is provided on the first conductive type substrate 2, the first conductive type drift region 3 concentration of about 1 × 1014~ 5 × 1016cm-3The specific concentration can be optimized according to the pressure requirements of the cell structure. A second conductive type well region 7, a second conductivity type enhancement region 9, and a high concentration first conductivity type source region 8 are sequentially provided above the first conductivity type drift region 3. The concentration range of the second conductivity type well region 7 is 1 × 1016~ 5 × 1018cm-3The concentration of the first conductivity type source region 8 is greater than or equal to 1 × 1019cm-3, The concentration of the second conductivity type enhancement zone 9 is greater than 5 × 1018cm-3.
[0124]In this embodiment, the second conductivity type well region 7 is disposed to be separated from the main groove, and the side of the well region is completely covered by the source area, such asFigure 5.
[0125]The gate structure includes a polysilicon trench gate structure;
[0126]Between the second conductivity type well region 7 and the main trench, the first conductive type drift region 3 is provided with a gate trench that is separated from the main groove, wherein the gate trench is far from the main trench. The wall portion on one side is simultaneously in contact with the first conductivity type source region 8, the second conductivity type well region 7, and the first conductivity type drift region 3;
[0127]The gate insulating layer 6 of the groove gate structure is disposed on the bottom and wall portion of the gate trench, and the polysilicon gate 5 and the first conductive type source region of the trench gate structure in the gate trench. 8, the second conductivity type well region 7 and the first conductivity type drift region 3 isolate.
[0128]In this embodiment, the polysilicon gate 5 is disposed in the trench, and the specifically is set,
[0129]The polysilicon gate 5 is provided with a gate insulating layer 6 and the first conductivity type source region 8, the second conductivity type well region 7, and the first conductivity type drift region 3 for isolation. The upper portion of the polycrystalline silicon gate 5 is provided with an interlayer medium 13 to isolate the source block metal 12;
[0130]The gate insulating layer 6 is simultaneously in contact with the first conductivity type source region 8, the second conductivity type well region 7, the first conductivity type drift region 3; the source metal 10 is enhanced from the first conductive type source region 8, the second conductivity type District 9 simultaneously in direct contact.
[0131]Further, the present invention also sets the second conductivity type well region in the local area of the Schottky Fire 4 and the first conductive type drift region 3, which reduces the leakage current when the Schottky knot is reversed, and the device is improved. Electrical performance.
[0132]The specific arrangement is provided as follows, and the second conductivity type well region 7 is disposed in contact with the main groove, and the second conductive type well region 7 is not completely covered by the first conductivity type source region 8, such asFigure 5-1.
[0133]The gate structure includes a polysilicon trench gate structure;
[0134]The surface of the second conductivity type source region 8 is not completely covered by the first conductive type source region 8, and the surface of the second conductivity type well region 7 is provided with a gate separated by the main groove. The polar groove, wherein the depth of the gate trench is greater than the depth of the second conductivity type well region 7, and the gate trench is remote from the wall portion of the main trench and the first conductivity type source region 8, second The conductive type well region 7 and the first conductivity type drift region 3 are simultaneously in contact.
[0135]The gate insulating layer 6 of the groove gate structure is disposed on the bottom and wall portion of the gate trench, and the polysilicon gate 5 and the first conductive type source region of the trench gate structure in the gate trench. 8, the second conductivity type well region 7 and the first conductivity type drift region 3 isolate.
[0136]In this embodiment, the gate insulating layer 6 and the polysilicon gate 5 divided into two portions are symmetric distribution in the Schottky 4 sides; wherein the polysilicon gate 5 is n-type, polycrystalline silicon gate 5 concentration concentration concentration ≥1 × 1018cm-3The gate insulating layer 6 has a thickness of ≥ 40 nm. The MOSFET device of this embodiment can reduce the input capacitance of the MOSFET device to further reduce the switch loss of the MOSFET device.
[0137]The source metal 10 and the Schottky Fire 4 form an ohmic contact with the semiconductor material, respectively, and the source metal ohmic contact material is disposed to have a metal or alloy having a low contact resistivity, preferably aluminum. The Schott Foundation Contact Materials can be selected from metal or alloys, preferably titanium, nickel. The source metal 10 and the Schott Fire 4 are connected by the surface secondary metal source block metal 12, the source block metal 12, the Schott Foundation 4, the source metal 10 and the polysilicon gate 5, the first conductivity type source The area 8 is isolated from the interlayer medium 13, and the interlayer medium 13 is oxide or nitride, and the structure isFigure 5 orFigure 5-1 Indicated.
[0138]In this embodiment, the SBD integrated in the MOSFET device is set in the JFET area, and since the MOSFET device is shared with the SBD, the use efficiency of the cell structure active region is improved, and the overall power density of the MOSFET device is improved.
[0139]In the present embodiment, a drain metal 11 is provided below the first conductive type substrate 3, and the drain metal 11 material is a metal or alloy having a low contact resistivity, preferably aluminum.
[0140]In the present embodiment, the main groove shape is arranged to be symmetrical, preferably, the specific shape is provided as a rectangular shape, the like, the like, the like, the semicircular, semi-elliptical, the Schott Fire 4 also sets The shape corresponding to the main trench structure.
[0141]Specifically, the drain metal 11, a first conductive type substrate 2, a first conductivity type drift region 3, a second conductivity type well region 7, a Schott Fire 4, constitutes an SBD built into a MOSFET device. It can be used as a renewal diode in the MOSFET device to make the MOSFET device module package without additional packaging SBD, and there is no additional bonding step, which reduces the package cost of the device, and reduces stray inductance. At the same time, since the SBD is integrated in the cell structure of the MOSFET device, the opening of the PIN diode in the MOSFET device can be effectively suppressed, thereby improving the bipolar injection effect, improving the long-term use of the MOSFET device.
[0142]In this embodiment, the SBD integrated by the MOSFET device is located in the JFET area, and the active region efficiency of the cell structure is improved, and the overall power density of the MOSFET device is further improved.
[0143]Further, the SBD of the present embodiment is integrated into the main groove of the JFET region, which can simultaneously implement the MOSFET device and the SBD's compromise relationship between the MOSFET device pond state current and block voltage.
[0144]In this embodiment, the cellular shape of the integrated SBD splitting gate silicon carbide MOSFET device can be provided as a strip type, which is easy to use a suitable process process to produce production, such asFigure 6 Indicated;
[0145]In the present embodiment, the cellular shape of the integral cell structure of the splitting gate silicon carbide MOSFET device integrated SBD can also be provided as a polygonal shape, preferably, is provided as a hexagonal, five-sided, four-sided shape, which is advantageous Different process processes are mass-produced, such asFigure 7 Indicated.
[0146]In summary,
[0147]1. The present invention is operatively connected by integrating SBD in silicon carbide MOSFET device cells, and the Schottky metal and source metal are effectively connected to make the module package without additional packaging SBD, reduce the package cost, and reduce spurious dissemination. inductance. Integrated SBD can effectively inhibit the opening of the PIN diode in the MOSFET device, improve the bipolar injection effect, and improve the reliability of the MOSFET device for a long time.
[0148]In addition, the JFET region and terminal area of the SBD and MOSFET device shared cell structure also increases the use area of the cell structure active region, thereby improving the use efficiency of the cell structure active zone, further improving the overall power density of the MOSFET device, improvement Electrical performance of MOSFET devices.
[0149]2, the present invention can simultaneously realize the multi-modular current and blocking voltage of the MOSFET device and the SBD in the cell structure surface in the cell structure of the MOSFET device. . Further, the present invention reduces the input capacitance of the MOSFET device by realizing the polysilicon gate splitting gate structure, further reduces the switching loss of the MOSFET device. The present invention also provides an ohmic contact of the source metal by providing a second conductive type enhancement zone above the second conductive type well region on both sides of the cell structure, and avoids the parasitic bipolar transistor (BJT) trigger. Further, the present invention also sets the second conductivity type well region in a local area in contact with the first conductivity type drift region, which reduces the leakage current at the time of reverse bias of the Schottky knot, improve the electrical device of the device. performance.
[0150]Further, in other embodiments, the present invention is equally applicable to the second conductivity type channel MOSFET device.
