Two-dimensional ferroelectric semiconductor channel ferroelectric dielectric layer field effect transistor and preparation method thereof
A technology of field effect transistors and semiconductors, applied in the field of effect transistors, can solve problems such as incompatibility with silicon-based semiconductor manufacturing processes, difficulty in achieving stable non-volatile storage, and prolonging the remnant polarization of ferroelectrics, achieving good application prospects and improving Device stability, the effect of reducing remanent polarization loss
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Publication Date
- 2021-06-15
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Abstract
Description
Technical field
[0001] The present invention belongs to the field of effector technology, and is specifically involved in a two-dimensional ferroelectric semiconductor channel ferroelectric layer effect tube and a preparation method thereof. Background technique
[0002] With the further development of artificial intelligence, massive data puts forward new challenges on the current computer storage capacity. In response to how to make fast, efficient, low power, anti-interference data storage, the iron farm effect transistors written by the flip-convertible electropper to realize the data, and the iron electric field effect tube is compared with the current commercial FERAM. Fast, low power, non-destructive reading data advantages.
[0003] As the foundation of future nano-electronic devices and large-scale integrated circuits, they own themselves with many excellent physical properties. The two-dimensional material itself is the atomic thickness, and naturally, it has a highly i...
Examples
Embodiment 1
[0028] A two-dimensional ferroelectric semiconductor channel ferroelectric layer effect tube, including an insulating substrate 1, a graphene gate 2, a graphene gate 2, respectively, a graphene gate 2, respectively, a two-dimensional ferroelectric The dielectric layer 3 and the metal gate 7 are provided with a two-dimensional ferroelectric semiconductor channel 4, and a two-dimensional ferric semiconductor channel 4 is provided on a two-dimensional ferroelectric semiconductor channel 4 respectively disposed a metal source 5 and a metal source 5. Metal drain 6, the metal source 5 is disposed on the right side of the metal drain 6, and the ferrous ferroelectric layer 3 and the two-dimensional ferroelectric semiconductor channel 4 are both positive.
[0029] Among them, the insulating substrate is a silica having a thickness of 285 nm; the graphene gate thickness is a single layer. The two-dimensional ferroelectric layer is made of copper indium phosphate sulfur, and the two-dimensio...
Embodiment 2
[0035] A two-dimensional ferroelectric semiconductor channel ferroelectric layer effect tube, including an insulating substrate 1, a graphene gate 2, a graphene gate 2, respectively, a graphene gate 2, respectively, a two-dimensional ferroelectric The dielectric layer 3 and the metal gate 7 are provided with a two-dimensional ferroelectric semiconductor channel 4, and a two-dimensional ferric semiconductor channel 4 is provided on a two-dimensional ferroelectric semiconductor channel 4 respectively disposed a metal source 5 and a metal source 5. Metal drain 6, the metal source 5 is disposed on the right side of the metal drain 6, and the ferrous ferroelectric layer 3 and the two-dimensional ferroelectric semiconductor channel 4 are both positive.
[0036] Among them, the insulating substrate is a silica having a thickness of 285 nm; the graphene gate thickness is a single layer. The two-dimensional ferrometer is made of copper indium phosphate sulfur, and the ferrous ferroelectric...
Embodiment 3
[0042] A two-dimensional ferroelectric semiconductor channel ferroelectric layer effect tube, including an insulating substrate 1, a graphene gate 2, a graphene gate 2, respectively, a graphene gate 2, respectively, a two-dimensional ferroelectric The dielectric layer 3 and the metal gate 7 are provided with a two-dimensional ferroelectric semiconductor channel 4, and a two-dimensional ferric semiconductor channel 4 is provided on a two-dimensional ferroelectric semiconductor channel 4 respectively disposed a metal source 5 and a metal source 5. Metal drain 6, the metal source 5 is disposed on the right side of the metal drain 6, and the ferrous ferroelectric layer 3 and the two-dimensional ferroelectric semiconductor channel 4 are both positive.
[0043] Wherein the insulating substrate is a silica having a thickness of 280 nm; the graphene gate thickness is 5 layers. The two-dimensional ferrotic layer is copper indium phosphate sulfur, and the ferrous ferroelectric semiconductor...