A kind of multi-chip packaging structure and manufacturing method thereof

A technology of multi-chip packaging and manufacturing methods, which is applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc., and can solve the problems that are difficult to meet the requirements of high performance, fast speed, multi-chip connection packaging and modularization, etc. problem, to achieve excellent heat dissipation effect, simple process structure, and short electrical path

Active Publication Date: 2022-07-22
FUDAN UNIV
View PDF3 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The traditional wire bonding (semiconductor bonding gold wire) and double-sided copper clip interconnection process are difficult to meet these high performance, fast speed, multi-chip connection packaging and modular requirements

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A kind of multi-chip packaging structure and manufacturing method thereof
  • A kind of multi-chip packaging structure and manufacturing method thereof
  • A kind of multi-chip packaging structure and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0042] In the embodiment, a novel chip packaging structure is provided, and the manufacturing method is as follows:

[0043] S101, providing and patterning the first metal substrate 101 and the second metal substrate 102 ( figure 1 ).

[0044] S102 , forming the first conductive layer 201 and the second conductive layer 202 on the first metal substrate 101 and the second metal substrate 102 , and placing the first chip 203 and the first chip 203 on the first conductive layer 201 and the second conductive layer 202 respectively Chip 204 ( figure 2 ).

[0045] S103 , on the first metal substrate 101 , the second metal substrate 102 , the side of the first conductive layer 201 , the side piece of the second conductive layer 202 , the first chip 203 , and the second chip 204 to make the first dielectric layer 301 and the second dielectric Layer 302 , a seventh conductive layer 303 and an eighth conductive layer 304 are formed on the first dielectric layer 301 and the second di...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses a multi-chip packaging structure and a manufacturing method thereof. In the present invention, copper substrate patterning, crystal solidification and conductive layer connection, dielectric material or top conductive layer production, medium patterning and hole opening, hole metallization, metal patterning on medium, production of intermediate medium layer, overall hole processing, hole metallization, Metallization or filling of dielectric, upper / lower metal patterning and other technological processes complete multi-core module packaging; the entire process of the present invention is completely compatible with PCB equipment and processes, and the obtained multi-core module has a simple structure, short electrical paths, and short heat dissipation paths. It has excellent low resistance characteristics and heat dissipation effect, and can achieve the effect of miniaturization and thinning.

Description

technical field [0001] The invention belongs to the technical field of chip packaging, and in particular relates to a multi-chip packaging structure and a manufacturing method thereof. Background technique [0002] MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, Metal-Oxide Semiconductor Field-Effect Transistor, referred to as Metal-Oxide Semiconductor Field-Effect Transistor), IGBT (Insulated Gate Bipolar Transistor, Insulated Gate Bipolar Transistor) power modules are used in almost all power In industrial products, power devices are developing towards high-performance, fast, multi-chip connection packages. The traditional wire bonding (semiconductor bonding alloy wire) and double-sided copper Clip interconnection process are difficult to meet these high-performance, high-speed, multi-chip connection packaging and modular requirements. In the future, the power semiconductor packaging process will develop to a more excellent PLFO (Panel level Fan-out, board leve...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/56H01L21/50H01L23/31H01L23/48H01L23/367H01L25/07
CPCH01L21/56H01L25/50H01L23/3121H01L23/48H01L23/367H01L25/071H01L2224/18H01L2224/92244H01L2224/32245H01L2224/73267
Inventor 江京樊嘉杰张国旗
Owner FUDAN UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap