Packaging structure based on manifold channel cover plate, and preparation method thereof
A technology of packaging structure and channel cover, which is applied in the direction of semiconductor/solid-state device parts, semiconductor devices, electrical components, etc., can solve the problems of electrical failure of IC devices, large temperature rise of cooling working fluid, incompatibility, etc., to reduce temperature rise , High heat dissipation efficiency, prolonging the service life effect
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[0041] In a specific embodiment, the present invention provides a method for preparing a packaging structure based on a manifold channel cover plate, which includes:
[0042] A chip is provided and embedded microfluidic channels are fabricated on top of the substrate of the chip.
[0043] When the chip 100 is in a wafer state, before fabricating the embedded micro-channel 102 , the wafer thickness of the chip 100 is first reduced, such as to a thickness of 300-500 μm, preferably 350-450 μm. This thickness requires that the silicon remain robust and reliable even after the embedded microfluidics for heat dissipation are etched on top of the substrate. Then, the embedded micro-channel 102 is fabricated on the top of the substrate 101 of the chip 100 through the combination of the wafer photolithography process and the wafer etching process. The etching process includes conventional wet etching and dry etching, and dry etching can include ion milling etching, plasma etching and ...
Embodiment 1
[0056] A package module of the chip is provided, and an upper cover plate of the package module is removed to expose a thermal interface material (TIM) on the upper surface of the chip substrate. The TIM is removed by grinding to expose the substrate of the chip. Other electrical structures on the chip are protected by coating photoresist. Next, the embedded micro-channel 102 is fabricated on the top of the substrate through the combination of hard mask and etching process to obtain the following figure 2 structure shown.
[0057] A silicon substrate is provided, and the inflow channel 204, the outflow channel 205, the liquid inlet 201 and the liquid outlet 202 are etched on the silicon substrate to obtain the following: image 3 Cover plate 200 is shown.
[0058] in such as image 3 The back of the cover plate 200 shown is coated or dipped in a suitable thickness of low temperature curing epoxy adhesive, and as figure 2 The embedded microchannels in the chip shown are ...
Embodiment 2
[0062] According to the method described in Example 1, the difference is that a silicon substrate is provided, and Ti / Cu 100 / 300nm are prepared on the back of the silicon substrate by a physical vapor deposition (PVD) process as an adhesion layer and a seed layer, respectively. Afterwards, the inflow channel 204, the outflow channel 205, the liquid inlet 201 and the liquid outlet 202 are etched on the silicon substrate, and Cu / Sn 6 / 2 μm is electroplated on the seed layer after removing the photoresist to obtain a Cover plate 200 for the tube channel. Among them, the process sequence of PVD+etching+electroplating can ensure that there is no metal inside the manifold channel and reduce the impact on the flow. Then, in the figure 2 A Cu layer with a thickness of about 1 μm is directly prepared by a physical vapor deposition (PVD) process at the bonding interface of the shown structure to obtain a chip structure with solder. Finally, align the manifold channel portion of the co...
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