Preparation method of monolithic interlayer through hole

Abstract

The invention provides a preparation method of a monolithic interlayer through hole. The preparation method of the monolithic interlayer through hole comprises the following steps of (1) preparing a mask pattern, namely sequentially carrying out spin coating, pre-baking, exposure, development and hardening on a silicon wafer; (2) pre-treating a deoxidation layer, namely soaking the silicon wafer on which a mask pattern is formed in an acid solution, and removing an oxidized SiO2 film on the surface of the silicon wafer; (3) carrying out biochemical variable-temperature etching, namely soaking the silicon wafer of the deoxidation layer in biochemical etching liquid, and performing biochemical variable-temperature etching to form the monolithic interlayer through hole, wherein the biochemical etching solution is an etching solution containing alkali-producing anaerobic bacteria. According to the method for manufacturing the monolithic interlayer through hole based on a biochemical mode, on the premise that the good etching effect and the etching quality of the through hole can be guaranteed, various problems occurring in an existing etching method can be effectively eradicated.

Description

technical field [0001] The invention relates to the technical field of integrated circuit packaging, in particular to a method for preparing through holes between monolithic layers. Background technique [0002] With the continuous breakthrough of integrated semiconductor manufacturing process technology, the performance of integrated circuit devices has developed rapidly, and the corresponding microelectronic packaging technology has gradually become an important factor restricting the development of semiconductor technology. In order to achieve smaller size, faster processing speed and lower manufacturing cost of semiconductor devices. More and more advanced packaging technologies that go beyond traditional packaging concepts have been proposed. Among them, the three-dimensional packaging technology realizes interconnection and communication through interlayer interconnection, which effectively shortens the interconnection length, reduces the parasitic parameters of the i...

AI Technical Summary

Problems solved by technology

[0005] However, at present, ion beam etching (IBE), deep silicon etching (DRIE), reactive ion etching (RIE), focused ion beam etching (FIB), and inductive coupling (ICP) are commonly used for monolithic interlayer vias. Plasma etching usually has a certain inclination problem in the processing of micro-nano through holes; the etching rate will also be different in different grain regions, causing non-uniform etching surface problems; residual pollution of reactive gases after etching, etc.