Josephson junction meeting large wafer size, preparation method and application

Abstract

The invention provides a Josephson junction satisfying a large wafer size, a preparation method and an application. The Josephson junction is prepared by preparing a Ta (110) film on a substrate, preparing a superconducting circuit structure through photoetching, forming a lower electrode Ta (110) layer through mask photoetching, preparing a Ta2O5 oxide layer on the surface of the lower electrode Ta (110) layer as an intermediate layer, and forming an upper electrode Ta (110) layer through mask photoetching. The Ta (110) superconducting thin film is used as the lower electrode and the upper electrode of the Josephson junction, the Ta2O5 oxide layer on the surface of the Ta (110) superconducting thin film has the characteristics of compactness, stability and the like, passivation and optimization can be performed by adopting a piranha solution, photoetching residual glue is further removed, the stability of a superconducting circuit structure and the Josephson junction is ensured, the method has the characteristics of simple process steps, stability, controllability, high integration level and the like, and the method is suitable for large-scale production. Uniform and stable Josephson junctions in a large wafer size range can be prepared, and the method is suitable for regulation and control of Josephson junctions with different areas.

Description

technical field [0001] The invention belongs to the technical field of superconducting chips, and relates to a Josephson junction satisfying a large wafer size, a preparation method and an application. Background technique [0002] As the core basic component of quantum chips, the structure and fabrication process of superconducting Josephson junctions have been extensively studied. How to ensure and improve the performance of the Josephson junction and simplify its preparation process has become a research hotspot. At the same time, in order to promote the realization of universal quantum computing, it is also important to prepare a stable and scalable Josephson junction that meets the large wafer size. [0003] At present, the suspension gel structure and the double-tilt evaporation technology are still common techniques for preparing Josephson junctions. A typical example is based on aluminum (Al) / alumina (AlO x ) / Al superconducting Josephson junction. After long-term d...

AI Technical Summary

Problems solved by technology

However, the oblique coating method still has certain disadvantages, such as: the film thickness and resistance uniformity of the Josephson junction in the large wafer size range cannot be guaranteed, which is not conducive to high integration

At the same time, limited by the existence of the polymer material mask layer, the preparation of the Josephson junction region needs to be controlled at a low temperature range from room temperature to 200 °C, which cannot reach the optimal growth temperature of the superconducting film layer.

[0004] From the material point of view, Al has a low superconducting temperature and superconducting energy gap, which is easy to cause quasi-particle injection and increase loss

On the other hand, the chemical properties of Al are relatively active, and naturally oxidized AlO x Has a certain dielectric loss when working at low temperature

At the same time, although the oxide layer is relatively dense and can achieve a certain passivation protection for the junction area, it is still unstable in the atmospheric environment or in the photolithography process, and is prone to denaturation after being treated with moisture or chemical reagents, further increasing the dielectric strength. electrical loss and will change the critical current of the Josephson junction

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