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Laminated capacitor storage unit and its manufacturing method

A technology for stacked capacitors and memory cells, applied in capacitors, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as increased resistance, deterioration of signal-to-noise ratio, and increased cost

Inactive Publication Date: 2004-09-08
INFINEON TECHNOLOGIES NORTH AMERICA CORPORATION
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this diffusion barrier adds undesirable resistance to the connection between the two storage nodes
This resistor degrades the signal-to-noise ratio, thereby reducing overall yield and increasing cost

Method used

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  • Laminated capacitor storage unit and its manufacturing method
  • Laminated capacitor storage unit and its manufacturing method
  • Laminated capacitor storage unit and its manufacturing method

Examples

Experimental program
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Embodiment Construction

[0011] Now, referring to the accompanying drawings, figure 1 Shown is a portion of a silicon wafer (substrate) 10 which will eventually be cut into a plurality of silicon chips, each chip comprising a plurality of memory cells arranged in an array to form a DRAM. The portion shown would be that of a chip comprising on its top surface 11 a series of polysilicon plugs 12 each doped to be highly conductive. Each plug 12 is positioned so as to pass through an opening in the silicon oxide layer 14 extending over the top surface of the silicon chip and extends down and into the bottom of the source / drain regions 13 of the silicon transistors in the chip. block the connection. This area 13 functions as a storage node of the storage unit. Typically, there are also other n-type doped regions (not shown) along the top surface of the chip that function as source / drain regions for transistors. An insulating layer 16 , also typically silicon oxide, extends over the top surface of layer...

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PUM

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Abstract

A DRAM memory cell structure of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) and a stacked capacitor and a method for forming same facilitates low resistance contact between the source / drain of the transistor and a lower electrode of the capacitor. The method in its preferred embodiment uses platinum for the bottom electrode of the capacitor without the need for a diffusion barrier between it and a doped polysilicon plug used to contact the MOSFET. To this end, the formation of the contact is after the deposition of the high dielectric material, such as barium strontium titanate, used to form the dielectric of the capacitor. Also the bottom electrode of the capacitor is partially offset with respect to the polysilicon plug.

Description

technical field [0001] The present invention relates to the manufacture of semiconductor devices, and more particularly to such a device which utilizes a plurality of stacked layers on the top surface of a semiconductor chip to form a capacitor within which the capacitor will be connected in series connected to a region extending onto the top surface of the semiconductor chip. Background technique [0002] Currently, many semiconductor integrated circuit devices include capacitors as circuit elements. A typical example of such an integrated circuit device is a dynamic random access memory (DRAM), which utilizes a capacitor as a storage cell, as a storage element in series with a switch provided by a metal oxide semiconductor field effect transistor (MOSFET). Such memory cells are formed in a dense array in a semiconductor chip. In one popular form of DRAM, the memory cell's storage capacitor is formed as stacks on the top surface of a silicon chip, and the switch is a MOSF...

Claims

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Application Information

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IPC IPC(8): H01L27/105H01L21/02H01L21/768H01L21/8242H01L21/8246
CPCH01L28/60H01L27/1085H01L27/10852H01L28/55H01L21/768H10B12/03H10B12/033
Inventor J·联G·昆克尔
Owner INFINEON TECHNOLOGIES NORTH AMERICA CORPORATION