Process for preparing metallic interconnection wire

Abstract

The invention discloses a metal inner-wire making method, applied to a semiconductor substrate whose surface contains a low-dielectric constant dielectric layer. The method includes the steps: making a depositing process to develop a nonnitrogenous antireflection layer, using the mixed gas of the silicic and oxygenous gas and the hydrogen as the reaction gas; using an optical-resistant layer pattern as mask to etch the antireflection layer; and using the optical resistant layer and the antireflection layer pattern as mask to etch the dielectric layer, synchronously or then, adding a hydrogen electric-plasm process to obtain an interlayer window or groove.

Description

technical field [0001] The invention relates to a manufacturing technology of a semiconductor integrated circuit, and in particular to a manufacturing method of a metal interconnection. Background technique [0002] The manufacturing process of semiconductor integrated circuits is an extremely complex process, the purpose of which is to shrink and manufacture various electronic components and circuits required for a specific circuit on a small-area substrate. Wherein, each component must be electrically connected by an appropriate interconnection wire (interconnect) in order to exert the desired function. Generally, the so-called metallization process (metallization) of integrated circuits, in addition to making the wiring patterns of each layer, also uses the structure of contact / via to be used as between the contact area of ​​the component and the wiring, or between the multilayer wiring. channels of communication. In recent years, in order to cooperate with the developm...

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Problems solved by technology

In terms of etching, because there is no proper way to improve the etching selectivity between the photoresist layer and the anti-reflection layer, and the thickness of the photoresist is reduced, and the aspect ratio in the manufacturing process is getting larger and larger, resulting in serious loss of critical dimension and Problems such as the occurrence of striated in the etched layer

In the etching process of the general integrated circuit manufacturing process, since the etching selectivity between the photoresist layer and the etched layer is not large, the photoresist layer used as a mask will also be damaged during the etching process and the thickness will be reduced. resulting in poor etch selectivity and etch stop between the photoresist layer and the anti-reflection layer

[0004] like figure 1 As shown, generally existing on the substrate or semiconductor element 10, the dielectric layer 12 of low dielectric constant, when forming the anti-reflection layer 14 in the lithography and etching manufacturing process, usually use monosilane (SiH 4 ) and carbon dioxide as a precursor, and selectively use helium as a carrier gas to deposit an anti-reflection layer 14 with a high carbon content. However, when the photoresist layer 16 pattern is used as a mask to etch this high carbon content When etching the anti-reflective layer 14 and the dielectric layer 12, there is often a problem of etch stop, especially when the pattern density is relatively sparse in the isolation type via etch (iso via etch), which causes the difficulty of opening the via window.

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