Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors

Abstract

This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and / or minimize implant-induced amorphization (a potential problem for source / drain (S / D) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S / D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S / D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined with ex situ heat treatments in a “divided-dose-anneal-in-between” (DDAB) scheme that avoids the need for tooling capable of performing hot implants.

Description

FIELD OF THE INVENTION [0001] This invention generally relates to complementary metal oxide semiconductor (CMOS) circuits comprising field effect transistors (FETs) fabricated with one or more ion implantation steps. More particularly, it relates to the ways in which these ion implantation steps may be combined with in situ or ex situ heat treatments to avoid and / or minimize implant-induced amorphization (a potential problem for source / drain regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained source / drain regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded source / drain regions lattice mismatched with an underlying substrate layer). BACKGROUND OF THE INVENTION [0002] Historically, most performance improvements in semiconductor field-effect transistors (FET) have been achieved by scaling down the relative dimensions of the device. This trend is becoming increasingly more dif...

AI Technical Summary

Benefits of technology

[0013] The present invention teaches the use of ion implantation in combination with in situ or ex situ heat treatments as a method for avoiding or reducing ion implant-induced amorphization and ion implant-induced plastic relaxation.

[0019] In a second embodiment of the invention, ion implantation is combined with ex situ heat treatments in a “divided-dose-anneal-in-between” (DDAB) scheme that avoids the need for tooling capable of performing hot implants. In this embodiment, the desired total dose is divided into smaller sub-doses, each of which is below the threshold for amorphizing the entire thickness of the S / D regions (for the case of UTSOI) or generating significant strain relief (for the case of strained S / D regions). Annealing performed after each implant recrystallizes the amorphized regions by solid phase epitaxy and / or reduces damage accumulation to a negligible level.

Problems solved by technology

This trend is becoming increasingly more difficult to maintain as the devices reach their physical scaling limits.

However, the ion implantation steps used in fabricating the FETs relying on these enhancements present two particular challenges.

It is difficult to implant the desired concentration of certain dopant species in the S / D regions without amorphizing the entire SOI layer.

If there is no crystalline Si left under the amorphized S / D regions to act as a seed or template, the S / D recrystallization will be highly defective (and thus unsuitable for high performance devices).

This is undesirable because doped polycrystalline Si has a much higher resistance than crystalline Si having the same dopant density.

One of the primary challenges in using single-crystal strained regions as a stressor for the channel is to prevent the formation of strain relieving dislocations during strained region growth and subsequent processing.

Certain implantation conditions (particularly those involving heavy ions such as As+) can result in a significant and irreversible reduction in strain after a prescribed thermal treatment step called an “activation anneal.” Since the driving force for strain relaxation increases with strain, SiGe alloys with a high Ge content are particularly susceptible to undesired relaxation.

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