Defect pattern matching and verification in integrated circuit design and manufacturing

Abstract

A method is disclosed for correcting design defects in a circuit layout. The method includes storing first-level defect patterns in a first-level defect pattern library and identifying in a first circuit layout a first target that matches the shape of a first-level defect pattern in the first-level defect pattern library, and modifying the first target in the first circuit layout to produce a modified circuit layout. The method also includes storing second-level defect patterns in a second-level defect pattern library. The second-level defect patterns stored in the second-level defect pattern library are related to defects in circuit manufacturing. The first-level defect patterns are not stored in the second-level defect pattern library. A second target in the modified circuit layout is identified to increase manufacturing yield of the circuit layout. The second target substantially matches a second-level defect pattern in the second-level defect pattern library.

Description

CROSS REFERENCES TO RELATED APPLICATIONS[0001]The present application is a continuation application of and claims priority to U.S. patent application Ser. No. 11 / 670,975, titled “Pattern match based optical proximity correction and verification of integrated circuit layout”, filed on Feb. 3, 2007 by the present inventor, the contents of which are incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]The present disclosure relates to semiconductor device manufacturing, and more particularly, to defect pattern matching and verification in integrated circuit layout and manufacturing.[0003]The fabrication of integrated circuits on a semiconductor substrate typically includes multiple photolithography steps. A photolithography step is the image transfer step, which transfers a circuit layout through photo-mask to a silicon wafer. A photolithography process begins by applying a thin layer of a photo-resist material to the substrate surface of a silicon wafer. The photo-resist ...

AI Technical Summary

Benefits of technology

[0011]In yet another general aspect, the present invention relates to a method for applying optical proximity correction (OPC) to a circuit layout. The method includes storing a plurality of distinct defect patterns in a defect pattern library; identifying a defect target pattern in a first circuit layout using the plurality of distinct defect patterns in the defect pattern library to produce an identified defect target pattern that substantially matched one of the plurality of distinct defect patterns in the defect pattern library; replacing the identified defect pattern by a fix pattern stored in the defect pattern library in association with the identified distinct defect patterns; storing a plurality of distinct patterns in an OPC pattern library, wherein each of the distinct pattern includes a distinct primary target and one or more neighboring targets adjacent to the primary target; storing one or more post-OPC targets in association with one of the plurality of distinct patterns in the OPC pattern library, wherein the one or more post-OPC targets are configured to correct optical proximity effects of the associated distinct pattern; identifying in the first circuit layout a pattern that has substantially the same optical proximity environment as the one of the plurality of distinct patterns in the OPC pattern library; applying OPC to the identified pattern by replacing the distinct primary target and targets surrounding the distinct primary target in the identified pattern by one or more post-OPC targets associated with the one of the distinct pattern in the OPC pattern library; if a pattern in the first circuit layout does not match any of the plurality of distinct patterns in the OPC pattern library, simulating the optical proximity effect of the pattern in the first circuit layout; and developing one or more post-OPC targets to replace one or more targets in the pattern in the first circuit layout to correct the optical proximity effect of the pattern in the first circuit layout.

[0018]The disclosed system and methods can also enable efficient distributed computing for OPC and its verification. The disclosed OPC is conducted in a pattern by pattern basis, which makes it easy to distribute OPC jobs to different computer process units (CPUs). The workload for each CPU can be easily balanced with no overhead. The OPC processing performance can thus linearly increase as the number of CPUs is increased.

Problems solved by technology

The minimum feature size that can be accurately produced on a substrate is limited by the ability of the fabrication process to form an undistorted optical image of the mask pattern onto the substrate, by the chemical and physical interaction of the photo-resist with the developer, and by the uniformity of the subsequent process (e.g., etching or diffusion) that uses the patterned photo-resist.

The inconsistent line widths can then cause circuit components that should be identical to operate at different speeds, thereby creating problems with the overall operation of the integrated circuit.

Furthermore, pulling back of the line ends can cause connections to be missed or to be weakened and prone to failure.

For example, these distortions include line width variations dependent on pattern density that affect a device's speed of operation, and line end shortening that can break connections to contacts.

Determining the optimal type, size, and symmetry (or lack thereof) is very complex and depends on neighboring geometries and process parameters.

The detection of defective shapes that require OPC is very time consuming considering the huge number of electronic components and even larger number of shapes on a photo-mask.

Images