Enhanced etch stop capability during patterning of silicon nitride including layer stacks by providing a chemically formed oxide layer during semiconductor processing

Abstract

A gate electrode structure may be formed on the basis of a silicon nitride cap material in combination with a very thin yet uniform silicon oxide based etch stop material, which may be formed on the basis of a chemically driven oxidation process. Due to the reduced thickness, a pronounced material erosion, for instance, during a wet chemical cleaning process after gate patterning, may be avoided, thereby not unduly affecting the further processing, for instance with respect to forming an embedded strain-inducing semiconductor alloy, while nevertheless providing the desired etch stop capabilities during removing the silicon nitride cap material.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]Generally, the present disclosure relates to the fabrication of sophisticated integrated circuits including complex layer stacks, such as gate layer stacks of highly capacitive gate structures formed on the basis of a high-k gate dielectric and metal-containing electrode materials.[0003]2. Description of the Related Art[0004]The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. During the very complex fabrication process, typically, material systems have to be formed and patterned, for instance, by wet chemical processes and plasma assisted etch processes, wherein usually one or more material layers may be provided as sacrificial layers, while other materials may represent permanent materials in the form of cond...

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Benefits of technology

[0018]Generally, the present disclosure provides techniques in which a thin silicon dioxide based etch stop material may be provided with a high degree of controllability, thereby enabling efficient removal of a silicon nitride based sacrificial material layer. The reduced thickness and superior uniformity, for instance with respect to material composition and layer thickness, may thus allow the incorporation of a silicon nitride material in combination with an efficient etch stop material, wherein the presence of the etch stop material may not unduly affect the further processing of the device. In some illustrative aspects disclosed herein, the material system of a thin etch stop layer in combination with a silicon nitride based material may be applied to sophisticated ga

Problems solved by technology

Upon continuously reducing the feature sizes of circuit elements, however, the material systems may have to be provided with reduced thickness and additional complex processes may have to be applied, thereby resulting in an undue interaction of aggressive process environments with the delicate layers.

Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors.

Due to the very reduced critical dimensions of transistor elements, resulting in a gate length of 50 nm and less, however, a further gain in performance may be difficult to achieve since the controllability of a short channel length associated with the reduced gate length typically requires, among other things, an appropriate adaptation of the thickness of the gate dielectric material, which, however, may result, in addition to increased process complexity in view of depositing the gate dielectric material and patterning the silicon gate electrode material, in a very pronounced increase of leakage currents, as the charge carriers may readily tunnel into and through the very thin silicon dioxide based gate dielectric material.

The pronounced notches 1

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