Method of fabricating ultra short gate length thin film transistors using optical lithography

Abstract

A method is provided for fabricating an ultra short gate length thin film transistor. A plurality of layers is deposited on a substrate including a refractory metal and a first and second photosensitive material. The second material is sensitive to longer wavelength optical radiation than the first material and the first material is not soluble in chemicals used to develop or strip the second material. A source contact pattern is defined in the second material to mask the first photosensitive material. The first material is processed to produce an undercut of the first material with respect to the second material. A metal layer is deposited at a normal incidence on the second material and an exposed portion of the refractory metal. The second material is removed. Exposed portions of the refractory metal corresponding to the undercut of the first material are removed to form a gap in the refractory metal.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is related to U.S. patent application Ser. No. 14 / 249,983, filed on even date herewith by Burhan Bayraktaroglu and Kevin Leedy, and entitled “Metal Oxide Thin Film Transistor Fabrication Method” (AFD 1293), the entirety of which is incorporated by reference herein.RIGHTS OF THE GOVERNMENT[0002]The invention described herein may be manufactured and used by or for the Government of the United States for all governmental purposes without the payment of any royalty.BACKGROUND OF THE INVENTION[0003]1. Field of the Invention[0004]The present invention relates to methods for forming transistors, and more particularly to methods for forming thin film transistors.[0005]2. Description of the Related Art[0006]Thin film transistors (TFT) are the basic building blocks of large area electronic circuits such as those used in the backplanes of active matrix liquid crystal displays (AMLCD) of the type often used in flat panel monitors and...

AI Technical Summary

Benefits of technology

This invention relates to a method of making thin film transistors with very small gate lengths. The method involves depositing layers of insulating material and metal on a substrate, and selectively removing portions of the metal layer. A second photosensitive material is then deposited and patterned to act as a mask for the first photosensitive material. The first photosensitive material is processed to create an undercut in it, and the exposed parts of the second photosensitive material are removed to form a gap in the metal layer. A metal layer is then deposited and patterned. The first and second photosensitive materials are removed. Overall, this method allows for the fabrication of thin film transistors with ultra-short gate lengths.

Problems solved by technology

Conventional transistors made on single crystal substrates cannot generally be used in these unique applications.

Transistors made from a-Si and p-Si, however, suffer from a number of deficiencies including low electron mobility, light sensitive operation, limited switching ratios, and / or poor threshold voltage uniformity.

These deficiencies make a-Si TFTs generally unsuitable for the current generation of display circuit applications that demand higher switching speeds and accuracy.

Photolithography, which is the main technology used in defining electrode dimensions for TFTs, is limited in scope to fabrication line widths larger than 1 micrometer.

These conditions cannot be maintained for thin film electronics and therefore only large gate lengths have been possible in the past.

This is especially true for metal oxide TFTs, whose fabrication technology is less mature than Si.

A major difficulty in metal oxide TFT manufacturing is the fabrication of source 16 and drain 18 contact metals over a semiconductor channel layer 20.

There are multiple sources of damage in conventional processes.

One source of damage is the chemicals used in lithography techniques.

Both the photoresist and the developer can damage the semiconductor surface by etching it or by contaminating it.

There are at least two sources of damage in this method.

First, the surface may be contaminated by the residue of the metal or the etchant due to incomplete metal removal.

Second, most chemicals used for etching the metal layer also causes etching of the semiconductor surface.

Even oxidizing chemicals such as hydrogen peroxide alone can damage ZnO surface.

The physical mask layer fabrication method has severe limitations in the feature sizes that can be used.

Instead of the desired dimensions in micrometers, this method is only capable of producing devices with feature sizes of millimeters.

The placement accuracy of the physical mask over the wafer is not well controlled resulting in gross errors in registering contact layers with respect to gate metal.

The edges of metal lines fabricated in this method have poor definition due to shadowing effects and result in uncontrolled device parameters.

This method adds several fabrication steps in manufacturing and results in degradation of device performance due to damaged layers or contamination resulting from additional processing steps.

The fabrication and the removal of this protective layer complicate the process and introduce sources of fabrication uncertainties across the wafer.

Apart from the fact that such etching conditions produce contaminated surface, they also result in uneven etch rates across the wafer.

The resulting device characteristics are therefore not uniform across the wafer.

However, it is well known that ZnO fabricated on top of metal layers often produces non-ohmic or high resistivity electrical properties, unlike the low resistivity ohmic properties of ZnO layers that are contacted from the top surface.

However, these approaches introduce an additional process step which can be a source of additional surface damage to the semiconductor layer.

Also, the positioning approach may additional introduce alignment errors in both X and Y dimensions so that across the wafer there may be rotational misalignments.

These sophisticated lithography techniques are slow, expensive and generally not compatible with the thin film electronics produced over large area substrates.

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