Semiconductor device including gate electrode for applying tensile stress to silicon substrate, and method of manufacturing the same

Abstract

A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source / drain region of the nMOS transistor, whereby the gate electrode (14) is amorphized. Subsequently, a silicon oxide film (40) is provided to cover the gate electrode (14), at a temperature which is less than the one at which recrystallization of the gate electrode (14) occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode (14), and high tensile stress is applied to a channel region under the gate electrode (14). As a result, carrier mobility of the nMOS transistor is enhanced.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to a semiconductor including a MOS (metal oxide semiconductor) field effect transistor, and method of manufacturing the same.[0003]2. Description of the Background Art[0004]For a MOS field effect transistor (MOS transistor), increase in drain current as a driving current is one of the ways of improving characteristic of this MOS transistor. Carrier mobility is one of the determinants of drain current. The carrier mobility is virtually controlled by a substrate material, and therefore, it can hardly be changed. On the other hand, it has been found that scattering probability and effective mass of carriers are altered by the change in lattice spacing of substrate atoms, allowing change of carrier mobility.[0005]SiGe has wider lattice spacing than Si. In a substrate including SiGe and Si stacked thereon, the lattice spacing of the upper-layer Si is widened accordingly. The substrate including ...

AI Technical Summary

Benefits of technology

[0013]It is therefore an object of the present invention to provide a semiconductor device allowing improvement in carrier mobility by applying tensile stress only to a channel region of a desired MOS transistor, and allowing simplification of manufacturing steps. It is still an object of the present invention to provide a method of this semiconductor device.

[0015]Tensile stress is applied to a region in the silicon substrate defined under a predetermined gate electrode. Therefore, lattice spacing is widened in this region of the silicon substrate. When this gate electrode is applied to an nMOS transistor, for example, enhancement of carrier mobility can be provided, thus contributing to performance improvement of the nMOS transistor.

[0017]Compressive residual stress is exerted on a predetermined gate electrode as internal stress therein, to apply tensile stress to a region in the silicon substrate defined under the gate electrode. Therefore, lattice spacing is widened in this region of the silicon substrate. When this gate electrode is applied to an nMOS transistor, for example, enhancement of carrier mobility can be provided, thus contributing to performance improvement of the nMOS transistor. Further, a mass number of ion to be implanted may vary according to the type of the gate electrode, or a part of the predetermined film on the predetermined gate electrode may be removed prior to thermal processing. Therefore, even when a plurality of gate electrodes are formed in the same step, only a desired gate electrode can easily be subjected to high compressive stress exerted thereon. As a result, simplification of the manufacturing steps is provided.

Problems solved by technology

On the other hand, the strained silicon substrate encounters the problems as follows which result from use of SiGe as a substrate material: crystal defect and deterioration in surface roughness caused by SiGe, rise in substrate temperature due to low heat conductivity of SiGe, increase in short-channel effect in a p-channel MOS transistor covering band discontinuity at an interface between SiGe and Si, or the like.

Other problems involved therein associated with process steps include inapplicability to STI (shallow trench isolation) technique, or insufficient activation annealing, for example.

In view of this, for actually using the strained silicon substrate in LSIs, there remain a lot of problems to be solved.

As a result, a gate electrode of the nMOS transistor and that of the pMOS transistor cannot be provided in the same process step, causing complication of the manufacturing steps.

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