Incorporation of nitrogen into high k dielectric film

a dielectric film and nitrogen technology, applied in the field of thin dielectric films, can solve the problems of long overall deposition time, increased fabrication cost, and reduced throughput, and the semiconductor industry is very sensitive to fabrication cos

Inactive Publication Date: 2005-11-01
ASM IP HLDG BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Slow nucleation entails longer overall deposition times, lower throughput and consequently greater fabrication costs.
The semiconductor industry is very sensitive to fabrication costs.
Accordingly, any increase in wafer throughput, at any stage of processing, translates to reduced production costs and higher margins.
This additional step unfortunately complicates the process flow, requires adjustment of the doping concentrations at the dielectric-electrode interface to ensure the desired work function for the transistor, and does not necessarily guarantee rapid and uniform nucleation.
Ultrathin gate oxides (less than 7 nm), however, have been found to exhibit high defect densities, including pinholes, charge trapping states, and susceptibility to hot carrier injection effects.
Such high defect densities lead to leakage currents through the gate dielectric and rapid device breakdown unacceptable for circuit designs with less than 0.25 μm gate spacing, i.e., sub-quarter-micron technology.
While care under laboratory conditions can be used to control defect densities, such control has been difficult to achieve under commercial volume fabrication conditions.
Moreover, even if the integrity of the oxide is perfectly maintained, quantum-mechanical effects set fundamental limits on the scaling of gate oxide.
Another problem with thin gate oxides is their susceptibility to dopant diffusion from the overlying gate electrode.
As the gate oxide thickness is scaled down, boron can easily penetrate through the gate oxide, resulting in instabilities in device properties.
Boron penetration into gate dielectrics has such undesirable consequences as positive shifts in threshold voltage, increases in sub-threshold swing, increases in charge trapping, decreases in low-field hole mobility, and degradation of current drive due to polysilicon depletion in p-MOSFETs.
However, the interfaces between silicon nitride films and the underlying semiconductor substrate are generally of poor quality, resulting in a high density of charge trapping sites and pinholes, and attendant current leakage.
Conventional methods of incorporating nitrogen into silicon oxide gate dielectrics are difficult to control, however, particularly for ultra-thin gate dielectrics of future generation devices
While exhibiting greatly increased dielectric strength, these materials have been difficult to integrate with existing fabrication technology.

Method used

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  • Incorporation of nitrogen into high k dielectric film
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Embodiment Construction

[0033]While the preferred embodiments are described in the context of transistor gate stacks, the skilled artisan will readily appreciate that the principles disclosed herein have application to a variety of contexts in which thin high k materials require a graded composition, particularly those having special interface needs. An example of such a context is in the formation of capacitors including high k dielectrics, proposed for high density memory cells in random access memory (RAM) arrays. The methods described herein are particularly advantageous for maintaining the stability of and preventing diffusion to or from high k materials.

[0034]Conventional gate electrode deposition over high k gate dielectrics has been found to result in poor electrical performance of the resultant devices. In order to increase the reliability and yield of the integrated circuits including high k dielectrics, the present invention provides a varied composition for a high k dielectric, whereby nitrogen...

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Abstract

A high k dielectric film and methods for forming the same are disclosed. The high k material includes two peaks of impurity concentration, particularly nitrogen, such as at a lower interface and upper interface, making the layer particularly suitable for transistor gate dielectric applications. The methods of formation include low temperature processes, particularly CVD using a remote plasma generator and atomic layer deposition using selective incorporation of nitrogen in the cyclic process. Advantageously, nitrogen levels are tailored during the deposition process and temperatures are low enough to avoid interdiffusion and allow maintenance of the desired impurity profile.

Description

REFERENCE TO RELATED APPLICATIONS[0001]The present application claims priority under 35 U.S.C. §119(e) to U.S. provisional application No. 60 / 326,830, filed Oct. 2, 2001.FIELD OF THE INVENTION[0002]The present invention relates generally to thin dielectric films in integrated circuits, and more particularly to nitrogen incorporation into high k gate dielectric films.BACKGROUND OF THE INVENTION[0003]Integrated circuit design is constantly being scaled down in pursuit of faster circuit operation and lower power consumption. Scaled dimensions in a circuit design generally requires attendant changes in fabrication processing.[0004]A basic building block of integrated circuits is the thin film transistor (TFT). As is known in the art, the transistor typically includes a gate electrode separated from a semiconductor layer or substrate by a thin gate dielectric material. Although a common acronym for state-of-the-art transistors is MOS, for metal-oxide-silicon, the material of choice for t...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): C23C16/30C23C16/448C23C16/452C23C16/455H01L21/28H01L29/40H01L21/02H01L21/318H01L21/314H01L29/51H01L21/316C23C16/40
CPCC23C16/308C23C16/455H01L21/28017H01L21/28185H01L21/28194H01L21/28202H01L21/3144H01L21/31604H01L21/31683H01L21/318H01L29/517C23C16/452Y10T428/12021H01L29/518Y10S438/932H01L2924/0002Y10T428/12458H01L2924/00Y10T428/31678H01L21/02189H01L21/02183H01L21/0228H01L21/02181H01L21/02197H01L21/02192H01L21/02178
Inventor SHERO, ERIC J.POMAREDE, CHRISTOPHE
Owner ASM IP HLDG BV
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