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Method for manufacturing PMOS transistor and PMOS transistor

A manufacturing method and transistor technology, applied in the manufacture of PMOS transistors, in the field of PMOS transistors, can solve the problems of deterioration of negative bias temperature stability, deterioration of MOS transistor performance, deterioration of drain current of MOS transistors, etc. Small, NBTI improvement effect

Active Publication Date: 2012-08-22
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this method, the holes flowing in the wire channel at the junction of the semiconductor substrate and the gate dielectric layer are hindered, so that the drain current flowing through the MOS transistor with temperature changes deteriorates, that is, the negative bias temperature stability ( NBTI) variation
[0005] Therefore, the problem in the above method is mainly that the NBTI of the MOS transistor is poor, and secondly, the gate leakage current makes the performance of the MOS transistor worse.

Method used

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  • Method for manufacturing PMOS transistor and PMOS transistor
  • Method for manufacturing PMOS transistor and PMOS transistor
  • Method for manufacturing PMOS transistor and PMOS transistor

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0065] Please refer to figure 2 .

[0066] S110: Provide a semiconductor substrate.

[0067] Such as image 3 As shown, a semiconductor substrate 100 is provided, and the semiconductor substrate 100 can be single crystal silicon, polycrystalline silicon or amorphous silicon; the semiconductor substrate 100 can also be silicon, germanium, gallium arsenide or silicon germanium compound; The semiconductor substrate 100 may also have an epitaxial layer or a silicon-on-insulator structure; the semiconductor substrate 100 may also be made of other semiconductor materials, which will not be listed here.

[0068] There may be a P well in the semiconductor substrate 100, and the P well may be formed by methods known to those skilled in the art, for example, on the semiconductor substrate 100, a region for forming the P well is first defined by a photolithography process , and then perform ion implantation to form a P well, and the implanted ions are P-type ions, such as boron ions....

Embodiment 2

[0084] Please refer to Figure 3-Figure 5 .

[0085] S210: Provide a semiconductor substrate.

[0086] This step is the same as step S110 and will not be repeated here.

[0087] S220: forming a gate oxide layer on the semiconductor substrate.

[0088] This step is the same as step S120 and will not be repeated here.

[0089] S230: Doping F ions into the gate oxide layer 102 .

[0090] Therefore, in this embodiment, the gate oxide layer 102 is doped with F ions, so that the F ions enter the gate oxide layer 102 and generate Si-F bonds at the junction 101 between the gate oxide layer 102 and the semiconductor substrate 100, because The Si-F bond is very stable, so the interface state changes less when the temperature changes.

[0091] At the same time, because there is a nitrogen-containing thin layer 106 on the surface of the gate oxide layer 102 , this layer makes it difficult for boron ions to pass through when F ions enter the gate oxide layer 102 through the nitrogen-c...

Embodiment 3

[0100] Such as Figure 4 As shown, the present invention also provides a PMOS transistor, including a semiconductor substrate 100 with a gate on the semiconductor substrate 100, and the gate includes a gate oxide layer 102 and a gate conductor on the gate oxide layer 102. Layer 104 has a source region 110 and a drain region 112 in the semiconductor substrate 100 on both sides of the gate, and the interface 101 between the gate oxide layer 102 and the semiconductor substrate 100 has Si-F chemical bonds.

[0101] In addition, there may be a nitrogen-containing thin layer 106 at the interface of the gate oxide layer 102 in contact with the gate conductive layer 104 .

[0102] Because the Si-F bond is very stable, the interface state is stabilized, thereby increasing the NBTI. Moreover, because there is a nitrogen-containing thin layer 106 at the junction of the gate oxide layer 102 and the gate conductive layer 104, the penetration and diffusion of P-type ions are reduced, the g...

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Abstract

The invention discloses a method for manufacturing a PMOS transistor and the PMOS transistor manufactured by the method, wherein the method comprises the following steps of: providing a semiconductor substrate; forming a gate oxide layer on the semiconductor substrate; forming a gate conductive layer on the gate oxide layer; doping F ions into the gate oxide layer through the gate conductive layer; etching the gate conductive layer and the gate oxide layer to form a grid; and forming a source electrode area and a drain electrode area in the semiconductor substrates on two sides of the grid. The method for manufacturing the PMOS transistor improves NBTI and the performance of the PMOS transistor.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a PMOS transistor and the PMOS transistor. Background technique [0002] In the existing MOS transistor manufacturing technology, usually a gate oxide layer is first formed on the semiconductor substrate, a gate conductive layer is formed on the gate oxide layer, and then the gate is formed by etching the gate conductive layer and the gate oxide layer, and then the Ion implantation into the substrate on both sides of the gate forms a source region and a drain region, thereby forming a MOS transistor. Wherein, the gate oxide layer is usually formed by oxide, such as silicon dioxide SiO 2 Or doped silica. In the manufacturing process of MOS transistors, in order to reduce the resistance of the gate, the gate conductive layer is usually doped after the gate conductive layer is formed, for example, implanting P-type boron into the gate ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L21/28H01L29/78H01L29/51
Inventor 居建华
Owner SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP
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