Realization method and device of multiphase filter structure

A technology of polyphase filter and filter, applied in the direction of impedance network, digital technology network, electrical components, etc., can solve the problems of efficiency bottleneck, low efficiency, poor flexibility, etc., and achieve the effect of ensuring real-time generation and saving hardware resources

Inactive Publication Date: 2011-01-26
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0013] 1. Low efficiency: Traditional methods often require multiple clock cycles to complete the sorting and output of a set of data vectors, thus becoming an efficiency bottleneck
Although increasing the operating clock frequency can increase the processing speed, it will cause deterioration of stability and power consumption. If the operating frequency of the device has reached the upper limit at this time, the throughput requirement cannot be met.
[0014] 2. Poor flexibility: The traditional method can only achieve sorting for a specific extraction or interpolation rate (parameter). If the parameter needs to be changed, it can only be realized by switching different polyphase filter structures or sorters, such as Figure 13 As shown, and this will greatly increase hardware overhead, increase power consumption and cost
[0015] As people's requirements for processing efficiency, flexibility, power consumption and cost of electronic systems are getting higher and higher, the variable sampling rate signal processing algorithm based on the traditional polyphase filter structure implementation scheme has become increasingly unable to meet the requirements of digital communication and electronic countermeasures. , digital multimedia and other fields

Method used

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  • Realization method and device of multiphase filter structure
  • Realization method and device of multiphase filter structure
  • Realization method and device of multiphase filter structure

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specific Embodiment 1

[0078] The specific structure of the device is as Figure 16 As shown, it includes the following parts:

[0079] (1) The clock source provides a clock clk_f synchronized with the highest sampling clock of the input digital signal;

[0080] (2) Data cache memory array, referred to as data cache array, it contains M+1 capacity of D MAX The readable and writable memory of: RAM(0), RAM(1), ..., RAM(M).

[0081](3) Multiplexer, the unit is connected to the data input port, the control unit, the data buffer array, and the weighted sum unit. Specifically, there are the following ports: data input port In; multiplexing state control port S connected to the control unit, data buffer array control signal input port WR, AddrD_WR, RD, AddrD_RD; control signal output port Addr_m, WRm connected to the data buffer array , RDm, data input port RAM(m)_Din, data output port RAM(m)_Dout,; data vector output port x connected to the weighted summation unit 1 , x 2 ,...,x M . The gating mode...

specific Embodiment 2

[0102] The structure of the device is as Figure 23 As shown, it contains the following parts:

[0103] (1) The clock source, which provides the clock clk_f with the same frequency as the highest input data rate;

[0104] (2) A multi-tap high-order delay line, which is implemented by a shift register or a first-in-first-out (FIFO) memory, corresponding to K possible values ​​of D, there are K groups of tap sequences on the high-order delay line, and the tap positions are 0, D, 2D, ..., (M-1)D, where D ∈ {D 1 ,D 2 ,...,D K}, the total order of the multi-tap high-order delay line is (M-1)D MAX .

[0105] (3) Multiplexer, its gating mode setting port SEL is connected to the control unit, all taps of the multi-tap high-order delay line at the input port are connected, and the output port is connected to the data vector input port x of the weighted summation unit 1 , x 2 ,...,x M connected. When the value on SEL is k (or D K ), the multiplexer takes the tap sequence 0 of ...

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Abstract

The invention discloses a realization method of a multiphase filter structure with synchronous arithmetic capability and real-time and variable orders, which realizes multiphase filtering operation and sampling rate transform on the basis of the scheme that structural repeatability of a branch filter in the multiphase filter structure is used, and a time-division multiplex kernel weighing summation unit is adopted. On the one hand, the scheme causes the multiphase filter structure to have synchronous data processing and throughput capacity with a working clock; on the other hand, the extract or interpolation rate of the multiphase filter structure can be dynamically changed by the online configuration of storage depth of data packet caching and the related operational control parameters, thus the multiphase filter structure has a function of the real-time and variable orders without additional hardware cost.

Description

technical field [0001] The invention belongs to the technical field of digital signal processing, and relates to the realization of a polyphase filter structure, more specifically, to a method and device for efficiently realizing a polyphase filter structure with synchronous operation capability and variable order. Background technique [0002] Digital signal processing is based on sampling and quantizing analog signals in the physical world. The sampling rate of digital signals usually depends on the physical characteristics of analog signals and the processing capabilities of the system. In the fields of digital communication, radar and electronic reconnaissance, instrumentation, digital audio and video, automatic control and other fields, the signals processed by the front and rear ends of the electronic system often have different physical characteristics (such as bandwidth, center frequency, etc.). A high digital signal sampling rate can greatly improve the processing e...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03H17/02
Inventor 何子述赵中原张建中程婷贾可新
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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