Low-pressure CMP (Chemico-mechanical Polishing) method for grand-scale integrated circuit copper wiring surface

A large-scale integrated circuit and low-voltage chemical technology, which is applied in chemical instruments and methods, circuits, and other chemical processes, can solve problems such as surface scratches, edge collapse, and material damage, and achieve good dispersion, low hardness, and pollution small effect

Inactive Publication Date: 2011-02-09
TIANJIN HEBEI UNIV OF TECH ASSET MANAGEMENT LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to overcome the above disadvantages, in order to solve the high efficiency of the polishing rate, while avoiding problems such as surface scratches, edge collapse, material damage, etc., to provide a simple, high-efficiency and low-cost VLSI copper wiring Surface low pressure chemical mechanical polishing method

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0029] Polishing liquid ratio and copper wiring low pressure CMP technology polishing process parameters requirements:

[0030] Prepare copper wiring CMP polishing solution 3135g: select 1200g nano-silica sol (15-20nm), the concentration of abrasive is 4-50wt%, put 1800g deionized water while stirring, then take 15gFA / OII type chelating agent, 30gFA / O Surfactant and 90 g of oxidizing agent were added to the above liquid with stirring. Adjust the pH value to 9-13, and stir evenly to obtain 3135 g of copper wiring polishing liquid.

[0031] The chelating agent used is FA / OII type chelating agent: ethylenediaminetetraacetic acid tetrakis (tetrahydroxyethylethylenediamine).

[0032] The active agent is FA / O surfactant, O π -7((C 10 h 21 -C 6 h 4 -O-CH 2 CH 2 O) 7 -H), O π -10 ((C 10 h 21 -C 6 h 4 -O-CH 2 CH 2 O) 10 -H), O-20 (C 12-18 h 25-37 -C 6 h 4 -O-CH 2 CH 2 O) 70 -H), a type of JFC.

[0033] The oxidant used is soluble under alkaline conditions as H...

Embodiment 2

[0038] Polishing liquid ratio and copper wiring low pressure CMP technology polishing process parameters requirements:

[0039]Prepare copper wiring CMP polishing solution 3240g: select 2000g nano-silica sol (20-30nm), the concentration of abrasive is 4-50wt%, add 1000g deionized water while stirring, then take 90gFA / OII type chelating agent, 120gFA / O Active agent and 30 g of oxidizing agent were added to the above liquid with stirring. Adjust the pH value to 9-13, and stir evenly to obtain 3240 g of copper wiring polishing liquid.

[0040] The polishing process is: pressure 2 KPa, flow rate 120ml / l, rotation speed 60rpm / min, temperature 50°C, polishing time 10min.

[0041] The polishing rate is 863nm / min, the non-uniformity of the polishing rate is controlled at 0.07, the surface has no scratches, and the roughness is 0.5nm.

[0042] Others are with embodiment 1.

Embodiment 3

[0044] Polishing liquid ratio and copper wiring low pressure CMP technology polishing process parameters requirements:

[0045] Prepare 3210g of copper wiring CMP polishing solution: select 1500g of nano-silica sol (30-40nm), the concentration of abrasive is 4-50wt%, put 1500g of deionized water while stirring, and then take 90gFA / OII type chelating agent, 30gFA / O Active agent and 90 g of oxidizing agent were added to the above liquid with stirring. Adjust the pH value to 9-13, and stir evenly to obtain 3000 g of copper wiring polishing liquid.

[0046] The polishing process is: pressure 2 KPa, flow rate 250ml / l, rotation speed 60rpm / min, temperature 20°C, polishing time 10min.

[0047] The polishing rate is 1174nm / min, the non-uniformity of the polishing rate is controlled at 0.03 without scratches on the surface, and the roughness is 0.2nm.

[0048] Others are with embodiment 1.

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Abstract

The invention relates to a low-pressure CMP (Chemico-mechanical Polishing) method for grand-scale integrated circuit copper wiring surface, comprising the following steps of: (1) preparing a polishing solution by uniformly mixing the following components in percentage by weight: 35-80% of nano SiO2 abrasive material, 12-60% of deionized water, 1-3% of oxidizing agent, 1-4% of activating agent and 0.5-1.5% of FA / OII type chelating agent; and (2) setting polishing technique parameters, wherein the polishing pressure is 2-5KPa, the polishing temperature is 20-50 DEG C, the flow rate is 120-250ml / min, and the rotating speed is 30-60rpm / min. The oxidizing agent in the polishing solution is used for oxidizing the copper, and the FA / OII type chelating agent self with extremely strong chelating capability quickly reacts with the oxidized copper to generate soluble chelate fast removing from the copper surface, thereby avoiding the situation of removing the surface copper depending on the mechanical friction mainly and realizing the purpose of copper polishing under low mechanical strength. The removal of materials in the chelating process is realized by breaking down molecular bond, which has small damage on the material surface; in addition, the influence of mechanical action on the polishing speed is compensated by reinforcing the CMP chemical action under low pressure.

Description

technical field [0001] The invention relates to a wafer surface polishing method, in particular to a low-pressure chemical-mechanical polishing method for copper wiring surfaces of ultra-large-scale integrated circuits. Background technique [0002] Metal copper has low resistivity, excellent anti-electromigration characteristics and low thermal sensitivity, which produces a small RC delay and can improve the reliability of the circuit. Copper wires replace traditional aluminum wires and become an ideal material for interconnection wires. [0003] With the reduction of device geometry, the number of metal layers and the increase of silicon substrate diameter, the degree of planarization of each layer has become one of the important factors affecting the etching line width of integrated circuits, and has become a bottleneck for the further development of microelectronics. Chemical mechanical polishing is by far the best technique for providing global planarization of multilay...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): B24B37/04H01L21/304
CPCC09G1/02H01L21/3212C09K3/1463
Inventor 刘玉岭刘效岩田军
Owner TIANJIN HEBEI UNIV OF TECH ASSET MANAGEMENT LTD
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