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Self-formed gradient Zr/ZrN double layer diffusion barrier layer and preparation method thereof

A barrier layer, double-layer technology, used in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, electrical components, etc., can solve the problems of poor adhesion, Cu interconnects are easily oxidized, etc., and achieve good adhesion. The effect of resistance and low resistivity

Inactive Publication Date: 2012-05-02
XI AN JIAOTONG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The technical problem to be solved by the present invention is to provide a self-forming gradient Zr / ZrN double-layer diffusion barrier and its preparation method to solve the problem that Cu interconnects are easily oxidized under low temperature and air, and SiO 2 And most of the problems such as poor adhesion of dielectric materials, the barrier film material of the present invention is formed by the optimized combination of amorphous Zr layer and ZrN two layers, which can fully meet the requirements of ultra-large-scale Cu interconnection diffusion barrier film

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0017] With a silicon wafer as the substrate, the Ar / N 2 In a gas atmosphere, a 10nm-thick nanocrystalline ZrN film was deposited by reactive sputtering; then in an Ar gas atmosphere, a 30nm-thick co-magnetron sputtering was carried out using a Zr sheet and a Cu sheet with a diameter×thickness of Φ50×3mm as sputtering targets Cu(Zr) alloy thin film; then a layer of 300nm thick pure Cu is plated on the surface of Cu(Zr) alloy thin film as an interconnection line to form a Cu / Cu(Zr) / ZrN / Si stack system. The total flow rate of sputtering gas is 30sccm, and the sputtering pressure is 0.3Pa; during reactive deposition of ZrN, N 2 N in / Ar mixed gas 2 The partial pressure is 0.03Pa, the partial pressure of Ar is 0.27Pa, the negative bias voltage of 100V is applied to the substrate, the power of the Zr target is 100-150W, and the deposition time is 10min; the power of Cu and Zr targets for co-depositing Cu(Zr) alloy is 150W respectively and 30W; the power for depositing pure Cu is ...

Embodiment 2

[0020] With a silicon wafer as the substrate, the Ar / N 2 In the gas atmosphere, a 5nm thick nanocrystalline ZrN film was deposited by reactive sputtering; then in an Ar gas atmosphere, a 20nm thick Zr sheet and a Cu sheet with a diameter×thickness of Φ50×3mm were used as sputtering targets for co-magnetron sputtering Cu(Zr) alloy thin film; then a 200nm thick layer of pure Cu is plated on the surface of Cu(Zr) alloy thin film as an interconnection line to form a Cu / Cu(Zr) / ZrN / Si stack system. The total flow rate of sputtering gas is 30sccm, and the sputtering pressure is 0.3Pa; during reactive deposition of ZrN, N 2 N in / Ar mixed gas 2 The partial pressure is 0.045Pa, the partial pressure of Ar is 0.255Pa, the negative bias voltage of 100V is applied to the substrate, the power of the Zr target is 100-150W, and the deposition time is 5min; the power of Cu and Zr targets for co-deposition of Cu(Zr) alloy is 150W respectively and 30W, the power for depositing pure Cu is 150W....

Embodiment 3

[0023] With a silicon wafer with a silicon dioxide oxide layer as the substrate, the Ar / N 2 In the gas atmosphere, a 4nm thick nanocrystalline ZrN film was deposited by reactive sputtering; then in an Ar gas atmosphere, a 20nm thick Zr sheet and a Cu sheet with a diameter×thickness of Φ50×3mm were used as sputtering targets for co-magnetron sputtering Cu(Zr) alloy film; then a layer of 200nm thick pure Cu is plated on the surface of Cu(Zr) alloy film as an interconnection line to form Cu / Cu(Zr) / ZrN / SiO 2 / Si stacking system. The total flow rate of sputtering gas is 30sccm, and the sputtering pressure is 0.3Pa; during reactive deposition of ZrN, N 2 N in / Ar mixed gas 2 The partial pressure is 0.09Pa, the Ar partial pressure is 0.21Pa, the negative bias voltage of 100V is applied to the substrate, the Zr target power is 100-150W, and the deposition time is 5min; the power of Cu and Zr targets for co-depositing Cu(Zr) alloy is 150W respectively and 30W, the power for depositi...

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Abstract

The invention provides a self-formed gradient Zr / ZrN double layer diffusion barrier layer and a preparation method thereof. A diffusion barrier layer comprises: a substrate, a Cu(Zr) alloy film which is deposited on the substrate and is taken as a seed layer and a self-precipitation layer, a nanocrystalline ZrN which is implanted between the substrate and the Cu(Zr) alloy film and is taken as a pre-barrier and a pure copper interconnection wire deposited on an upper layer of the Cu(Zr) alloy film. The double layer barrier layer formed in the invention is continuous, uniform and compact. A thickness can be controlled in several nanometers. A resistance is low, heat stability is high and adhesion is good. A performance requirement of a hyper-scale integrated circuit to the Cu interconnection diffusion barrier layer can be satisfied.

Description

technical field [0001] The invention relates to a material for a diffusion barrier layer of an integrated circuit Cu interconnection system, in particular to a self-forming gradient Zr / ZrN double-layer diffusion barrier layer and a preparation method thereof. Background technique [0002] With the development of VLSI, Cu with low resistivity replaces Al as the interconnect material. However, Cu interconnect lines are easily diffused and polluted, and are easily oxidized at low temperature and air. 2 And the poor adhesion of most dielectric materials. Need to be in Cu and Si, SiO 2 Add an appropriate diffusion barrier layer (Diffusion Barrier Layer) between the dielectric layer to prevent the oxidation of the Cu film and block the diffusion of Cu atoms, increase the bonding strength between Cu and the dielectric layer, thereby improving the interface characteristics of Cu interconnection, reducing electromigration, and improving reliability. [0003] As the feature size of...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/532H01L21/768
Inventor 宋忠孝何国华李雁淮钱旦范丽娜吴汇焱徐可为
Owner XI AN JIAOTONG UNIV