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Method for manufacturing solar cell

A technology of solar cells and manufacturing methods, applied in the direction of final product manufacturing, sustainable manufacturing/processing, semiconductor/solid-state device manufacturing, etc., which can solve problems such as substrate quality degradation, interface defects, and time-consuming, so as to prevent substrate quality from deteriorating , fewer processing steps, and the effect of suppressing the generation of defects

Inactive Publication Date: 2015-02-11
MITSUBISHI ELECTRIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0010] In addition, in the method described in Patent Document 2, there is a problem that as a mask material for suppressing the diffusion of dopant impurities into the light-receiving region of the semiconductor substrate, it is necessary to set a mask that can withstand the high temperature during diffusion. It takes time when the mask is used and when the impurity is diffused multiple times, and the quality of the substrate is deteriorated due to these high-temperature treatments, and hydrogen leaks from the interface between the substrate and the mask, thereby generating interface defects.

Method used

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  • Method for manufacturing solar cell
  • Method for manufacturing solar cell
  • Method for manufacturing solar cell

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Experimental program
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Embodiment approach 1

[0044] First, the structure of the solar cell used in Embodiment 1 will be described. Figure 1-1 to Figure 1-3 is a diagram schematically showing an example of the overall structure of a solar cell according to Embodiment 1 of the present invention, Picture 1-1 is the top view of the solar cell, Figure 1-2 is the back view of the solar cell, Figure 1-3 yes Figure 1-2 The A-A section diagram. in addition, figure 2 is an enlarged cross-sectional view schematically showing a part of the structure of a solar cell, and is Picture 1-1 The B-B section diagram.

[0045] In this solar cell 100, on the light-receiving surface side (hereinafter, also referred to as the surface side) of the P-type silicon substrate 101 as a semiconductor substrate, a concave portion 115 is provided corresponding to the formation position of the surface electrode 110, and other than the concave portion 115 The surface of the silicon substrate 101 is formed with an unillustrated textured structur...

Embodiment approach 2

[0078] Figure 4 It is a partial cross-sectional view schematically showing an example of the structure of the solar cell according to the second embodiment. The graph is also compatible with figure 2 Similarly, a part of the cross section in the direction perpendicular to the gate electrode is shown. The solar cell according to Embodiment 2 is formed by embedding the surface electrode 110 in the concave portion 115 formed on the surface of the silicon substrate 101, and the N-type diffusion layer 102 has the same concentration of N-type impurities in the light receiving portion and the concave portion 115. structure. In addition, the same reference numerals are assigned to the same components as those in Embodiment 1, and description thereof will be omitted. According to the structure of the solar cell according to Embodiment 2, a buried electrode thick in the depth direction and narrow in width is formed as the surface electrode 110 .

[0079] Next, a method of manufact...

Embodiment approach 3

[0109] In Embodiment 3, a mounting method in which terminals of element components are inserted into through holes of a printed circuit board and soldered will be described.

[0110] Figure 6 It is a partial cross-sectional view schematically showing an example of a connection state between a printed circuit board and a terminal of a circuit element component according to the third embodiment. This figure shows a part of the section along the printed wiring. In the printed wiring board 300 of the third embodiment, the printed wiring 302 of a predetermined shape is formed on the first main surface and the second main surface of the substrate 301, and at a predetermined position on the printed wiring 302, a through the through hole 315 of the substrate 301 . On the side surface inside the through hole 315, a copper wiring 303 for connecting the printed wiring on the first main surface and the second main surface is formed. In addition, around the through hole 315, a convex p...

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Abstract

Disclosed is a method for manufacturing a semiconductor device that is free from the occurrence of a deterioration in substrate quality and defects.  The method comprises the steps of forming concaves (115) on a P-type silicon substrate (101), forming an N-type diffusion layer (102) containing N-type impurities on the surface of the P-type silicon substrate (101), and exposing the area other than the concaves (115) in the P-type silicon substrate (101) to a treatment fluid of a gas phase or a liquid phase containing a chemical species that can be rendered active, whereby the surface of the assembly is treated to have properties different from the properties of the concaves (115).

Description

technical field [0001] The present invention relates to a method for manufacturing a semiconductor device, a printed circuit board, and a method for manufacturing the same. Background technique [0002] Photolithography is generally used for pattern formation in the manufacturing process of semiconductor devices, but when processing such as film formation is performed at the same position as the drawn pattern generated by photolithography, a self-alignment process that does not require alignment is preferable. Here, as an example of a self-alignment process in which an already formed pattern is used as a mask for a subsequent process, there are self-alignment silicides and the like. In this self-aligning silicide, metal silicide can be formed only on silicon that is not masked by a silicon oxide film or the like by utilizing the property that a clean silicon surface is easy to react with metal. By using the self-matching process, there is an advantage that a pattern drawing...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/306H01L31/04H05K1/02H05K3/34
CPCH01L31/1804Y02E10/547Y02P70/50
Inventor 新延大介西村邦彦松野繁
Owner MITSUBISHI ELECTRIC CORP