Sidewall preparation method for reducing coupling interference of metal oxide semiconductor field effect transistor (MOSFET)
A technology of coupling interference and sidewall, which is used in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., to improve integration and memory read and write rates, improve performance, and reduce coupling interference.
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
preparation example Construction
[0053] The preparation method of the low-K sidewall process that reduces MOSFET coupling interference of the present invention is as figure 2 Shown, this preparation method comprises the steps:
[0054] Step 1: forming a gate oxide layer on the semiconductor substrate;
[0055] Step 2: preparing a gate on the gate oxide layer;
[0056] Step 3: Depositing a low-K dielectric material on the gate and the semiconductor substrate, and performing carbon doping during the deposition process to form a low-K dielectric layer containing carbon material.
[0057] The process of preparing the gate oxide layer and the gate in step 1 and step 2 can be completed by using the preparation process in the prior art, so as to image 3 Another main unit structure of the CMOS device shown is the non-volatile memory unit as an example. It can be known that the non-volatile memory unit can be a floating gate type or a trap charge trapping type, which is different from a general MOS device only in ...
Embodiment 1
[0060] Conventional MOSFET sidewall is to deposit SiO2 and Si3N4 or both combination, and sidewall process of the present invention is: the present invention can deposit a SiO2 layer on grid gate and semiconductor silicon plate, and, in deposition process SiO2 The layer is doped with carbon to form a SiO2 layer with a lower dielectric constant, and the redundant SiO2 layer with a lower dielectric constant is etched away to form a SiO2 layer such as figure 1 shown by the low-k gate spacer 103 or image 3 The low-k gate spacer shown in 1. In another embodiment of the present invention, a SiO2 and Si3N4 layer is deposited on the gate and the semiconductor silicon plate, and the SiO2 and Si3N4 layers are carbon-doped during the deposition process, thereby forming SiO2 and Si3N4 with a lower dielectric constant layer, etch to remove excess low dielectric constant SiO2 and Si3N4 layers, thus forming such as figure 1 shown in the gate spacer 103 or image 3 Gate spacers shown in 1...
Embodiment 2
[0063] Step 3 may specifically include the following steps:
[0064] Step 31: Depositing and forming an inner layer of a carbon-doped low-K dielectric layer with a microporous structure on the gate and the semiconductor substrate, and using a self-aligned etching process to form the inner layer into a first sidewall layer;
[0065] Step 32: Deposit an outer layer made of SiO2, Si3N4 or a combination thereof on the first sidewall layer, and use a self-aligned etching process to form the outer layer into a second sidewall layer.
[0066] From the above steps 31 and 32, it can be seen that the low-K sidewalls for reducing MOSFET coupling interference use two layers of sidewalls inside and outside, that is, Carbon Doped Oxide (Carbon Doped Oxide) with a microporous structure with an ultra-low dielectric constant (ULK). , referred to as CDO) as the inner layer of the sidewall (for example, k is 2.5); and, in order to make the sidewall achieve a certain physical strength and make th...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More