Method for preparing sub-pixel structured planar InGaAs infrared detector chip
An infrared detector and sub-pixel technology, applied in electrical components, semiconductor devices, final product manufacturing, etc., can solve problems such as difficulty in suppression, reduce surface recombination, reduce diffusion thermal damage, and improve response rate and detection rate Effect
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[0046] The specific implementation method of the present invention will be further described in detail below in conjunction with the drawings and embodiments.
[0047] as attached figure 2 As shown, the epitaxial wafer used in this embodiment adopts metal-organic chemical vapor deposition (MOCVD) technology with a thickness of 300 μm and a carrier concentration > 3×10 18 cm -3 An N-type InP layer 2 with a thickness of 0.5 μm is sequentially grown on the N-type InP substrate 1, and the carrier concentration is >2×10 18 cm -3 InGaAs intrinsic absorption layer 3 with a thickness of 2.5 μm and a carrier concentration of 5×10 16 cm -3 ; N-type InP capping layer 4 with a thickness of 1 μm and a carrier concentration of 5×10 16 cm -3 . This embodiment includes a total of 10 sub-pixel diffusion window areas 6, each with a size of 25×500 μm 2 , with a pitch of 15 μm.
[0048] The specific preparation process steps of the chip of this embodiment are as follows:
[0049] 1) Cle...
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