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Strained SiGe return-type channel SOI (silicon on insulator) BiCMOS (bipolar complementary metal oxide semiconductor) integrated device and preparation method

An integrated device, channel direction technology, applied in semiconductor/solid-state device manufacturing, electrical solid-state devices, semiconductor devices and other directions, can solve the conditions that do not have the ability to replace silicon-based technology, limit the development of Si integrated circuit manufacturing technology, integration and Increased complexity, etc.

Inactive Publication Date: 2012-10-17
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, with the further increase of the scale of integrated circuits, the reduction of device feature size, the increase of integration and complexity, especially after the device feature size enters the nanometer scale, the limitations of materials and physical characteristics of Si CMOS devices have gradually emerged. out, limiting the further development of Si integrated circuits and their manufacturing processes
Although microelectronics has made great progress in the research and application of compound semiconductors and other new materials in some fields, it is far from having the conditions to replace silicon-based processes

Method used

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  • Strained SiGe return-type channel SOI (silicon on insulator) BiCMOS (bipolar complementary metal oxide semiconductor) integrated device and preparation method

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0130] Embodiment 1: The strained SiGe return type channel SOI BiCMOS integrated device and the circuit that the preparation conduction channel is 45nm, concrete steps are as follows:

[0131] Step 1, epitaxial material preparation.

[0132] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 400nm, and the upper material is doped with a concentration of 1×10 17 cm -3 N-type Si with a thickness of 150nm;

[0133] (1b) Using chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer with a thickness of 300nm on the upper layer of Si material at 750°C, as the collector region, and the doping concentration of this layer is 1× 10 17 cm -3 ;

[0134] (1c) Deposit a layer of SiO with a thickness of 300nm on the surface of the substrate at 800°C by chemical vapor deposition (CVD). 2 layer;

[0135] (1d) Deposit a SiN layer with a thickness of 200nm on the surface of...

Embodiment 2

[0208] Embodiment 2: The preparation of the strained SiGe back channel SOI BiCMOS integrated device and circuit with a conductive channel of 30nm, the specific steps are as follows:

[0209] Step 1, epitaxial material preparation.

[0210] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 350nm, and the upper material is doped with a concentration of 5×10 16 cm -3 N-type Si with a thickness of 120nm;

[0211] (1b) Using the chemical vapor deposition (CVD) method, at 700 ° C, grow a layer of N-type epitaxial Si layer with a thickness of 250 nm on the upper Si material, as the collector region, and the doping concentration of this layer is 5× 10 16 cm -3 ;

[0212](1c) Deposit a layer of SiO with a thickness of 240nm on the surface of the substrate at 700°C by chemical vapor deposition (CVD). 2 layer;

[0213] (1d) Deposit a layer of SiN with a thickness of 150 nm on the sur...

Embodiment 3

[0286] Embodiment 3: The preparation of the strained SiGe back channel SOI BiCMOS integrated device and circuit with a conductive channel of 22nm, the specific steps are as follows:

[0287] Step 1, epitaxial material preparation.

[0288] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , the thickness is 300nm, and the upper layer material is a doping concentration of 1×10 16 cm -3 N-type Si with a thickness of 100nm;

[0289] (1b) Using chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer with a thickness of 250nm on the upper Si material at 600°C, as the collector region, and the doping concentration of this layer is 1× 10 16 cm -3 ;

[0290] (1c) Deposit a layer of SiO with a thickness of 200nm on the surface of the substrate at 600°C by chemical vapor deposition (CVD). 2 layer;

[0291] (1d) Deposit a layer of SiN with a thickness of 100 nm on the surface of the sub...

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Abstract

The invention discloses a strained SiGe return-type channel SOI BiCMOS integrated device and a preparation method. The preparation method comprises growing N-Si on an SOI substrate as the collector region of the bipolar device, etching a base region by lithography, growing P-SiGe, i-Si and i-Poly-Si on the base region, preparing deep trench isolation, and preparing an emitter, a base and a collector to obtain a SiGe HBT (heterojunction bipolar transistor); etching the active region of an NMOS (n-type metal oxide semiconductor) device by lithography, and epitaxially growing five material layers in the active region to obtain the active region of the NMOS device; etching the active region of a PMOS (p-type metal oxide semiconductor) device by lithography, epitaxially growing three material layers on the active region to obtain the active region of the PMOS device, preparing the NMOS device, forming a virtual gate of the PMOS device, and implanting to form the source and drain of the PMOS device by self-alignment process; and etching the virtual gate to complete the preparation of the PMOS device, and preparing the strained SiGe return-type channel SOI BiCMOS integrated device and circuit with a conductive channel of 22 to 45nm of the MOS device. The preparation method provided by the invention adopts the self-alignment process and fully utilizes the characteristics of carrier mobility anisotropy of the strained SiGe material to prepare the performance-enhanced strained SiGe return-type channel SOI BiCMOS integrated circuit.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, in particular to a strained SiGe back channel SOI BiCMOS integrated device and a preparation method. Background technique [0002] Semiconductor integrated circuits are the foundation of the electronics industry, and people's huge demand for the electronics industry has prompted the rapid development of this field. In the past few decades, the rapid development of the electronics industry has had a huge impact on social development and national economy. At present, the electronics industry has become the largest industry in the world, occupying a large share in the global market, and its output value has exceeded 1 trillion US dollars. [0003] Si CMOS integrated circuits have the advantages of low power consumption, high integration, low noise and high reliability, and occupy a dominant position in the semiconductor integrated circuit industry. However, with the furth...

Claims

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Application Information

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IPC IPC(8): H01L27/12H01L21/84H01L21/28
Inventor 宋建军胡辉勇周春宇吕懿张鹤鸣宣荣喜舒斌郝跃
Owner XIDIAN UNIV
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