Strained SiGe return-type channel SOI (silicon on insulator) BiCMOS (bipolar complementary metal oxide semiconductor) integrated device and preparation method
An integrated device, channel direction technology, applied in semiconductor/solid-state device manufacturing, electrical solid-state devices, semiconductor devices and other directions, can solve the conditions that do not have the ability to replace silicon-based technology, limit the development of Si integrated circuit manufacturing technology, integration and Increased complexity, etc.
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Embodiment 1
[0130] Embodiment 1: The strained SiGe return type channel SOI BiCMOS integrated device and the circuit that the preparation conduction channel is 45nm, concrete steps are as follows:
[0131] Step 1, epitaxial material preparation.
[0132] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 400nm, and the upper material is doped with a concentration of 1×10 17 cm -3 N-type Si with a thickness of 150nm;
[0133] (1b) Using chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer with a thickness of 300nm on the upper layer of Si material at 750°C, as the collector region, and the doping concentration of this layer is 1× 10 17 cm -3 ;
[0134] (1c) Deposit a layer of SiO with a thickness of 300nm on the surface of the substrate at 800°C by chemical vapor deposition (CVD). 2 layer;
[0135] (1d) Deposit a SiN layer with a thickness of 200nm on the surface of...
Embodiment 2
[0208] Embodiment 2: The preparation of the strained SiGe back channel SOI BiCMOS integrated device and circuit with a conductive channel of 30nm, the specific steps are as follows:
[0209] Step 1, epitaxial material preparation.
[0210] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 350nm, and the upper material is doped with a concentration of 5×10 16 cm -3 N-type Si with a thickness of 120nm;
[0211] (1b) Using the chemical vapor deposition (CVD) method, at 700 ° C, grow a layer of N-type epitaxial Si layer with a thickness of 250 nm on the upper Si material, as the collector region, and the doping concentration of this layer is 5× 10 16 cm -3 ;
[0212](1c) Deposit a layer of SiO with a thickness of 240nm on the surface of the substrate at 700°C by chemical vapor deposition (CVD). 2 layer;
[0213] (1d) Deposit a layer of SiN with a thickness of 150 nm on the sur...
Embodiment 3
[0286] Embodiment 3: The preparation of the strained SiGe back channel SOI BiCMOS integrated device and circuit with a conductive channel of 22nm, the specific steps are as follows:
[0287] Step 1, epitaxial material preparation.
[0288] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , the thickness is 300nm, and the upper layer material is a doping concentration of 1×10 16 cm -3 N-type Si with a thickness of 100nm;
[0289] (1b) Using chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer with a thickness of 250nm on the upper Si material at 600°C, as the collector region, and the doping concentration of this layer is 1× 10 16 cm -3 ;
[0290] (1c) Deposit a layer of SiO with a thickness of 200nm on the surface of the substrate at 600°C by chemical vapor deposition (CVD). 2 layer;
[0291] (1d) Deposit a layer of SiN with a thickness of 100 nm on the surface of the sub...
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