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High-density silica back sealing process for heavily-doped-phosphorous monocrystalline silicon wafer

A silicon dioxide and silicon wafer technology, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as unsatisfactory requirements and insufficient compactness of silicon dioxide films, achieving strong practicability and improving Dense, highly feasible effect

Inactive Publication Date: 2013-03-13
TIANJIN ZHONGHUAN ADVANCED MATERIAL TECH
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AI Technical Summary

Problems solved by technology

In this case, the silicon dioxide film prepared by the traditional chemical vapor deposition (CVD—Chemical Vapor Deposition) method often cannot meet the requirements due to its insufficient compactness.

Method used

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Examples

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Embodiment

[0019] Example: 1) The thickness of 6 inches (150mm in diameter) after preparation for back damage and cleaning is 642μm, and the dopant is P, Single crystal silicon wafers with crystal orientation and resistivity of 0.0008-0.00018Ω·cm are used as raw materials; 2) The silicon wafers after back damage and cleaning are placed on the upper stage of the back sealer (the back sealer model is AMAYA A63007); 3) At this time, the silicon wafer is placed on the silicon carbide tray by the manipulator and transported to the reaction chamber; 4) Silane and oxygen are introduced into the reaction chamber, the concentration ratio of which is silane: oxygen = 1:10; 5) The heating temperature of the heating unit at the bottom of the silicon carbide tray is 700 ℃, and the silicon wafer is covered with a cooling water unit to keep the surface temperature of the silicon wafer at 430 ℃; 6) The reaction is carried out by the nozzle in the reaction chamber Substance silicon dioxide is deposited on...

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Abstract

The invention relates to a high-density silica back sealing process for a heavily-doped-phosphorous monocrystalline silicon wafer. The process comprises the following steps of: 1. preparing a silica film through a back sealing machine by adopting APCVD (Atmospheric Pressure Chemical Vapor Deposition); 2. annealing a wafer with silica by using a thermal annealing process during the manufacturing of a semiconductor; and 3. removing an oxidation layer from the facade and the edge of the wafer by using a method of removing an oxidation film in a scratch grinding manner or a manual film pasting manner. According to the invention, a monocrystalline silicon wafer back sealing material traditionally deposited by adopting CVD (Chemical Vapor Deposition) is enhanced by using the thermal annealing process during the manufacturing of the semiconductor, so that the compactness of the traditional CVD back sealing process is improved, and the requirement of an epitaxial process of a thick layer of the heavily-doped-phosphorous monocrystalline silicon wafer is satisfied. General-purpose equipment manufactured by the semiconductor is adopted by the thermal annealing process, so that the structure principle is simple. The back sealing process provided by the invention has high feasibility and strong practicability, thereby being suitable for large-scale industrial production.

Description

Technical field [0001] The invention relates to a back processing technology of a semiconductor silicon wafer, in particular to a high-density silicon dioxide back-sealing process for a heavily doped phosphorous monocrystalline silicon wafer. Background technique [0002] The processing of monocrystalline silicon wafers generally mainly includes slicing, chamfering, grinding, etching, back treatment, polishing, cleaning and other processes. The back treatment process generally includes back damage treatment, back sealing treatment and edge oxide film removal treatment, etc. . Back-seal processing is an important process for monocrystalline silicon wafer processing. The quality of the back cover plays a crucial role in the epitaxial process. This is because generally speaking, epitaxially deposited silicon wafers are heavily doped Miscellaneous, at the temperature of the epitaxial growth process (about 1100°C), the dopants of heavily doped silicon wafers will diffuse out of the h...

Claims

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Application Information

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IPC IPC(8): H01L21/02
Inventor 李满李家友齐呈跃王玮刘沛然
Owner TIANJIN ZHONGHUAN ADVANCED MATERIAL TECH
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