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Method of preparing groove discrete semiconductor device

A discrete device and semiconductor technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as poor terminal structure, poor device breakdown voltage and reliability, and difficult to generate

Inactive Publication Date: 2013-07-24
立新半导体有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In the existing trench power MOSFET design and manufacturing field, the base region and the source region of the MOSFET are introduced by the steps of base region mask and source region mask respectively. In order to reduce the manufacturing cost, some previous proposals, For example, the published US patent documents US20110233667, US20090085074, US20110233666, US077996427, etc., try to omit the manufacturing method of the mask step of the base region or the source region, the steps are relatively complicated and difficult to produce, and the terminal (termination) structure of the manufactured semiconductor device Not good, so that the breakdown voltage and reliability of the device are relatively poor

Method used

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  • Method of preparing groove discrete semiconductor device
  • Method of preparing groove discrete semiconductor device
  • Method of preparing groove discrete semiconductor device

Examples

Experimental program
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Embodiment 1

[0081] Such as figure 1 As shown, the epitaxial layer 200 is placed above the substrate 10. First, an oxide layer 400 (with a thickness of 0.3um to 1.5um oxide hard mask) is formed on the epitaxial layer by deposition or thermal growth, and then on the oxide layer A photoresist coating 1000 is deposited and then patterned through a trench mask to expose portions of the oxide layer.

[0082] Such as figure 2 As shown, after dry etching the oxide layer exposed by patterning the trench mask, the epitaxial layer is exposed, and then the photolithographic coating is removed.

[0083] Such as image 3 As shown, implant P-type dopants on the surface of the silicon wafer (the dose is 2e12 / cm 3 to 2e14 / cm 3 ), the part covered by the original oxide layer 400 has not been implanted, the part not covered by the original oxide layer, the P-type dopant will be injected into the surface of the epitaxial layer to form a P-type region, and the P-type dopant can be B11 (boron boron ).

...

Embodiment 2

[0098] The technical scheme of the present embodiment is roughly the same as that of embodiment 1, and its difference only lies in:

[0099] In the above example 1 Figure 5 Before etching the trench, first deposit a layer of oxide layer and seal the opening width of the trench mask in the oxide layer ranging from 0.2um to 0.6um. The width of the sealed opening can be 0.2um or 0.3um or 0.4um or 0.5um or 0.6um, depending on the preparation method, the advantage of this step is that some trench mask openings are implanted with P-type dopants (P-type 1 region) but not The trench is opened, the terminal structure of the device is better, so the breakdown voltage of the device is higher and more stable, and then the oxide layer is dry-etched to remove the oxide layer on the opening and expose the epitaxial layer on the opening; After etching the trench, only those openings that are not sealed by the precipitated oxide layer are opened. The trench (1.0um to 7.0um in depth and 0.2um...

Embodiment 3

[0101] The technical scheme of the present embodiment is roughly the same as that of embodiment 1, and its difference only lies in:

[0102] In the above example 1 Figure 15 Before etching the contact hole trench, first deposit a layer of (LPCVD) oxide layer, and then dry-etch the oxide layer to remove the oxide layer in the opening of the contact hole trench, exposing the epitaxial layer in the opening; etched contact hole trenches. Other steps are basically identical with embodiment 1, and the cross section of device is as follows Figure 19 shown.

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Abstract

The invention discloses a method of preparing a groove discrete semiconductor device. The method comprises the following steps: first, injecting P type dopant into an epitaxial layer of a substrate to form a P type area I by using a groove mask, and carrying out etching on the external layer to form a plurality of grid electrode grooves; then depositing interlamination media on the surface of the external layer, carrying out etching on the interlamination media by using a contact hole mask to form openings in the interlamination media, and injecting the P type dopant and N type dopant to the openings to form a P type area II and an N type source region respectively, wherein the P type area I and the P type area II are combined into a P type base region; then carrying out etching on the surface of the external layer to form contact hole grooves, and carrying out metal plugging filling on the contact hole grooves; and finally, depositing a metal layer on the surface of a device, carrying out metal etching by using metal mask to form a metal cushion layer and connection wires. By adopting the method of preparing the groove discrete semiconductor device, preparation procedures of base region masking and source region masking are eliminated, and the preparation cost of the device is made to be greatly reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor power discrete devices, in particular to a method for preparing a trench semiconductor power discrete device. Background technique [0002] At present, power MOSFET (Metal Oxide Semiconductor Field Effect Transistor, Metal Oxide Semiconductor Field Effect Transistor) has been widely used in various electronic and communication products, computers, consumer appliances, automobiles, etc. At the same time, it also has various applications in industry. [0003] Power semiconductor devices represented by power MOSFETs can effectively control high-frequency large currents due to their low on-resistance and high-speed switching. At the same time, power MOSFETs are being widely used as small power conversion components such as power amplifiers, power converters, low noise amplifiers, and some personal computer power supply switches and power circuits, which are characterized by low power consumption...

Claims

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Application Information

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IPC IPC(8): H01L21/336
Inventor 苏冠创
Owner 立新半导体有限公司
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