38results about How to "Omit the preparation process" patented technology

The invention discloses a packaging substrate as well as a manufacturing method and a base material thereof. The manufacturing method of the packaging substrate comprises the following steps: two metal layers are mutually laminated, and a dielectric layer is utilized to clad the two metal layers; next, layer increasing line structures are respectively formed at the two sides of the dielectric layer; and finally, the layer increasing line structures at the two sides of the dielectric layer are separated along the interface of the two metal layers so that two packaging substrates are formed. In the invention, the adhesion characteristics of the dielectric layer is utilized so that the two metal layers in the middle cannot be separated in the course of forming the layer increasing line structures in the initial stage, and the dielectric layer part around the two metal layers is cut off to successfully separate the two metal layers so that the manufacturing process is simplified, and the two metal layers in the middle can form a line layer, a metal lug or a supporting structure through the pattering manufacturing process and have no waste.

The invention relates to a Raised Pad manufacturing method, which comprises the steps of manufacturing an outer layer circuit, and the manufacturing of the outer layer circuit comprises the followingsteps of: S1, drilling the inner layer circuit of a PCB, entering a board electrical process, electroplating the whole board in an electroplating mode, and plating a layer of copper on the whole boardsurface and the wall of a drilled hole; S2, pressing a layer of photosensitive anti-corrosion film on the board surface subjected to plate electrification by using a hot roller film pressing machineto ensure the copper plating thickness; S3, manufacturing an outer layer circuit by adopting a developing machine, an etching machine and a film removing machine; S4, depositing a thin copper layer onthe independent units of the outer-layer circuit through copper deposition wires to enable the independent units to be connected together, and providing a conductor for subsequent electroplating; S5,pressing a layer of photosensitive anti-corrosion film on the board surface subjected to plate electrification by using a hot roller film pressing machine for manufacturing a PAD pattern for electroplating; and S6, placing the treated board on a copper plating wire to be subjected to copper plating operation, and obtaining the Raided Pad. The Raised Pad manufacturing method has the advantages ofthe simple process, low cost, high efficiency, the good product yield and the like.

The invention discloses a production method of an MLCC capacitor. The method comprises the following steps: (1) coating a copper foil / aluminum foil with a slurry formed by plastic particles and ceramic particles, and drying to obtain a copper foil composite layer / aluminum foil composite layer; (2) sequentially stacking the copper foil composite layers and the aluminum foil composite layers together at intervals, heating to a softening point of plastic, and rolling to obtain a multi-layer ceramic composite body; and (3) putting one end surface of a multi-layer ceramic composite into a diluted hydrochloric acid to dissolve the aluminum foil near the end surface, and leaving the copper foil; putting the other end surface into a concentrated nitric acid to dissolve the copper foil near the end surface, leaving the aluminum foil, and polishing to remove an aluminum passivation layer; and then, welding the two end surfaces with an external electrode by using tin so that the copper foils are mutually connected into a whole, and the aluminum foils are mutually connected into a whole, and obtaining the MLCC capacitor. According to the production method of the MLCC capacitor, the process is simplified, the energy is saved, and the quality problems of a short circuit, open circuit and the like caused by improper sintering of a nickel powder and a barium titanate powder are avoided.

The invention provides a manufacturing method of an array substrate. The method comprises the following steps of sequentially manufacturing a first metal layer, an insulating layer, an active layer and a second metal layer on the substrate; manufacturing a transparent conductive film on the substrate and covering the second metal layer by the transparent conductive film; coating the transparent conductive film with a third photoresist and covering a third mask on the third photoresist to photoetch a pattern on the third photoresist, wherein the projection of the second metal layer on the third photoresist is included in the pattern; and etching the transparent conductive film to form a transparent electrode layer and covering the second metal layer by the transparent electrode layer. According to the manufacturing method provided by the invention, the manufacturing cost of the array substrate is reduced, the manufacturing procedure of the array substrate is simplified and the production efficiency is improved. The array substrate and a liquid crystal display panel provided by the invention are relatively low in manufacturing cost.

The invention provides an array substrate and a display panel, and relates to the technical field of the display. The technological process of the display panel can be simplified. The array substrate comprises a substrate, and a gate metal layer, a gate insulating layer, a semiconductor active layer, a source drain metal layer, a barrier layer and a light shielding structure which are successively installed on the substrate; the gate metal layer comprises a bottom gate electrode and a grating line; the source drain metal layer comprises a source electrode, a drain electrode and a data line; and the light shielding structure comprises an electric electrode, and the electric electrode is electrically connected with the bottom gate electrode, wherein the light-proof light shielding structure is further used as a black matrix.

The embodiments of the present invention provide a fabrication method of a super-junction power device. The method includes the following steps that: a substrate is provided, and an epitaxial layer is grown on the surface of the substrate; a first P-type pillar and a second P-type pillar are fabricated on the epitaxial layer; ion implantation is performed on the surfaces of the first P-type pillar and the second P-type pillar, so that ion concentration on the surfaces of the first P-type pillar and the second P-type pillar can be decreased, and the depth of the ion implantation is smaller than the depth of the first P-type pillar and the second P-type pillar; source regions are fabricated in the first P-type pillar and the second P-type pillar, the depth of the source regions is greater than the depth of the ion implantation and is smaller than the depth of the first P-type pillar and the second P-type pillar; and the gate oxide layer, gate, dielectric layer and metal layer of the device are fabricated. With the method provided by the embodiments of the present invention adopted, the problem of charge imbalance between P-type pillars and an N-type epitaxial layer caused by a high-temperature drive-in process in a conventional process can be avoided, and the withstand voltage performance of the device can be improved.

The invention provides a method for producing nickel powder from pure nickel sulfate solution through direct deposition. The method comprises the following steps: adjusting the pH value of the pure nickel sulfate solution at a concentration more than 8g / L to between 2.0 and 7.2; and taking a Pb-Ag-Ca lead base alloy as an anode and a stainless steel plate as a cathode, performing electrolysis to deposit the nickel powder on the negative plate, wherein in the electrolysis, the current density is between 1,000 and 4,000A / M2, and the temperature of electrolyte solution is between 20 and 60DEG C.The granularity of the electrolytic nickel powder prepared by the method is less than 200 meshes, and the oxygen content is lower than 0.35 percent. The method has the advantages of simple process, short process flow, low production cost, energy efficiency and environmental protection, is suitable for directly preparing the electrolytic nickel powder from the pure nickel sulfate solution, is alsosuitable for directly preparing the electrolytic nickel powder from nickel solution recovered from nickel waste and purified, has realistic significance of recycling materials and protecting the environment, and is particularly suitable for environment-friendly enterprises in which the nickel-containing waste is subjected to various links of impurity removal to obtain nickel-containing solution.

The invention discloses a method of preparing a groove discrete semiconductor device. The method comprises the following steps: first, injecting P type dopant into an epitaxial layer of a substrate to form a P type area I by using a groove mask, and carrying out etching on the external layer to form a plurality of grid electrode grooves; then depositing interlamination media on the surface of the external layer, carrying out etching on the interlamination media by using a contact hole mask to form openings in the interlamination media, and injecting the P type dopant and N type dopant to the openings to form a P type area II and an N type source region respectively, wherein the P type area I and the P type area II are combined into a P type base region; then carrying out etching on the surface of the external layer to form contact hole grooves, and carrying out metal plugging filling on the contact hole grooves; and finally, depositing a metal layer on the surface of a device, carrying out metal etching by using metal mask to form a metal cushion layer and connection wires. By adopting the method of preparing the groove discrete semiconductor device, preparation procedures of base region masking and source region masking are eliminated, and the preparation cost of the device is made to be greatly reduced.

The invention discloses a preparation method of a trench semiconductor power device. The preparation method of the trench semiconductor power device includes a first step of injecting dopant into an epitaxial layer arranged on a substrate for two times to form P-type base regions and N-type base regions, and conducting corrosion on the epitaxial layer to form a plurality of grid trenches; a second step of depositing interlayer mediums on the epitaxial layer, conducting the corrosion on the interlayer mediums through a contact hole mask, conducting the corrosion on the interlayer mediums and the surface of the epitaxial layer through a contact hole mask to form contact trenches, and conducting metal plugging filling on the contact trenches; and a third step of depositing a metal layer on the surface of the discrete device, conducting metal corrosion through a metal mask and forming a metal substrate layer and a connecting wire. The preparation method of the trench semiconductor power device eliminates preparation procedures of a base region mask and a source region mask, and therefore the manufacturing cost of the power device is greatly reduced. In addition, original electrical characteristics of the power device cannot be influenced. The cost-performance ratio of the power device is improved. The performance, the quality and the reliability of the trench semiconductor power device are not influenced.

The invention discloses a preparation method of lactobacillus rhamnosus soybean milk direct vat set starter. Lactobacillus rhamnosus is subjected to high-density culture by a low-price enrichment medium, centrifugal concentration and separation, mixed dissolution with high-efficiency composite protective agent and lyophilization to prepare the lactobacillus casei soybean milk direct vat set starter. According to the preparation method, the viable organism of the prepared starter is over 1*10<11>cfu / g; after the starter is sealed under normal pressure and preserved at 4 DEG C for 1 year, the content of the viable organism is still over 10<10>cfu / g, and a higher fermentation activity is stilled maintained; and soybean milk is fermented at 37 DEG C with the inoculum size being lower than one ten-thousandth, and the milk can be cured after 4 to 5 hours, wherein the soybean yoghurt product fermented by the starter has the acidity being between 70oT and 80oT, the pH value being about 4.6, and good sense and flavor. The starter can be used in the fermented dairy products industry and vegetable protein processing industry.

The invention discloses an array electric fluid power printing head, which comprises an ink box, and a nozzle plate positioned at the middle part of the ink box and used for partitioning the cavity of the ink box into an upper cavity and a lower cavity; nozzle holes are distributed in the nozzle plate in an array mode, and the nozzle holes are communicated with the upper cavity and the lower cavity; the bottom of the lower part of the ink box is provided with ink outlets correspondingly arranged in an array; an upper electrode is arranged at the bottom of the nozzle plate, and a lower electrode is arranged at the bottom of the ink box, so that an electric field is formed in the lower cavity; and the ink in the upper cavity passes through the nozzle holes and enters the lower cavity, the ink forms jet under the action of the electric field of the lower cavity, and the ink is ejected for printing through the ink outlets. Because the electric fluid power printing principle is adopted in the array electric fluid power printing head, the jet diameter can reach 1 to 10 microns, and the jet is not affected by the diameter of a nozzle; and the array electric fluid power printing head has large jet dragging force, is suitable for high-viscosity solution, and does not destroy the material. The array electric fluid power printing head has the characteristics of simple structure, high printing precision and low cost, and has good industrial practicability.

The invention discloses a preparation method of a trench semiconductor power discrete device. The preparation method of the trench semiconductor power discrete device includes a first step of injecting P-type dopant into an epitaxial layer arranged on a substrate to form P-type base regions through a trench mask and conducting corrosion on the epitaxial layer to form a plurality of grid trenches; a second step of depositing interlayer mediums on the epitaxial layer, conducting the corrosion on the interlayer mediums through a contact hole mask, forming trenches in the interlayer mediums, injecting N-type dopant to form N-type source regions, conducting the corrosion on the surface of the epitaxial layer to form contact trenches, and conducting metal plugging filling on the contact trenches; and a third step of depositing a metal layer on the surface of the discrete device, conducting metal corrosion through a metal mask and forming a metal substrate layer and a connecting wire. The preparation method of the trench semiconductor power discrete device eliminates preparation procedures of a base region mask and a source region mask, and therefore the manufacturing cost of the discrete device is greatly reduced. In addition, original electrical characteristics of the discrete device cannot be influenced.

The conventional auxiliary rearview mirrors for automobile usually need an additional spring for claming to the rearview mirror, and a jaw for urging against one of the rearview mirrors, and the buffering members for securing the jaw, where these additional components all complicate the manufacturing process. According to this invention, the auxiliary rearview mirror includes a rearview mirror body installed on a front of the existing rearview mirror; a reflection mirror provided on a front of the rearview mirror body; a jaw provided on either a top or bottom of the back of the rearview mirror body; a freely movable jaw provided with another top or bottom of the back of the rearview mirror body; an annular portion provide to its center; springs provided on both ends for urging one of the jaws towards the other jaw; an urging portion urging against an outer periphery of the annular portion and provided on the rearview mirror body; and a separation-prevention annular portion provided at an outer side of the annular portion and covering an end of the annular portion. In addition, on the back of the rearview mirror is provided with a clamping portion. A resilient member is further provided. Guide walls formed with slits are provided on the opposing sides of the jaw face and facing each other, projections are provided to the jaw face, and projections are provided on its opposing sides for engaging the slits. The resilient members with indents at a lower portion engage the projections.

The invention discloses a method of preparing a trench semiconductor power discrete device. The method comprises the following steps of firstly injecting P-type doping agents into an epitaxial layer on a substrate through a trench mask to form P-type base regions, and then eroding the epitaxial layer to form a plurality of grid trenches; injecting N-type doping agents into side walls of the tops of the trenches to form N-type source regions; then, settlinginterlayer dielectric on the surface of the epitaxial layer, eroding the interlayer dielectric and the surface of the epitaxial layer to form contact trenches by means of a contact hole mask, and filling the contact trenches with metal plugs; and finally, settling a metal layer on the upper surface of the device, and conducting metal erosion through a metal mask to form a metal cushion layer and a connection line. By means of the preparing method, preparing processes of a base-region mask and a source-region mask are omitted, and therefore manufacturing cost of the device is greatly lowered; and meanwhile, original electrical characteristics of the device is not influenced, and therefore the price performance ratio of the device is increased.

The invention belongs to the technical field of solar cells, and provides a method for testing free carrier absorption loss and a cell sample, and the method comprises the steps: preparing a cell sample with a specific structure, the battery sample comprises a first region, a second region and a third region; the first region is provided with a first heavily-doped layer on the front surface and then a second heavily-doped layer on the rear surface; the third region is provided with a second heavily-doped layer on the front surface and then a second heavily-doped layer on the rear surface; testing the external quantum efficiency of the first area, the second area and the third area in the near-infrared band; obtaining integral current density values of the first region, the second region and the third region according to the external quantum efficiency and the AM1.5 G spectrum of the first region, the second region and the third region; and obtaining the free carrier absorption loss according to the integral current density values of the first region, the second region and the third region. The method is simpler in test, short in time consumption and low in cost, and can quickly and accurately realize quantitative detection of free carrier absorption loss.

The invention discloses a method for preparing an MLCC capacitor, comprising: (1) coating a slurry formed of plastic particles and ceramic particles on copper foil / aluminum foil, and drying to obtain a copper foil composite layer / aluminum foil composite layer; 2) Lay the copper foil composite layer and the aluminum foil composite layer together at intervals, heat to the softening point of the plastic, and then roll to obtain a multilayer ceramic composite body; (3) place one end of the multilayer ceramic composite body into dilute hydrochloric acid to dissolve the aluminum foil near the end face, and leave the copper foil; put the other end face into concentrated nitric acid to dissolve the copper foil near the end face, leave the aluminum foil, and polish to remove the aluminum passivation layer; then, the two end faces Solder with external electrodes with tin respectively, so that the copper foils are connected with each other and the aluminum foils are connected with each other as a whole to obtain an MLCC capacitor. The preparation method of the MLCC capacitor of the present invention not only simplifies the process, saves energy, but also avoids quality problems such as improper sintering of nickel powder and barium titanate powder, resulting in short circuit and open circuit.

The invention discloses a preparation method of lactobacillus casei soybean milk direct vat set starter. Lactobacillus casei is subjected to high-density culture by a low-price enrichment medium, centrifugal concentration and separation, mixed dissolution with high-efficiency composite protective agent and lyophilization to prepare the lactobacillus casei soybean milk direct vat set starter. According to the preparation method, the viable organism of the prepared starter is over 1*10<11>cfu / g; after the starter is sealed under normal pressure and preserved at 4 DEG C for 1 year, the content of the viable organism is still over 10<10>cfu / g, and a higher fermentation activity is stilled maintained; and soybean milk is fermented at 37 DEG C with the inoculum size being lower than one ten-thousandth, and the milk can be cured after 4 to 5 hours, wherein the soybean yoghurt product fermented by the starter has the acidity being between 70 oT and 80oT, the pH value being about 4.6, and good sense and flavor. The starter can be used in the fermented dairy products industry and vegetable protein processing industry.

The invention relates to an integrated high-flatness solar power generation integral roof and a quick integration method and belongs to the technical field of solar power generation. The integrated high-flatness solar power generation integral roof is characterized in that frameless photovoltaic modules and sealing adhesive tape wrapped on the four edges of each frameless photovoltaic module form photovoltaic modules; the upper end, the lower end, the left side and the right side of each photovoltaic module are all provided with pressing bars; a water channel is arranged below a connecting gap between the adjacent photovoltaic modules; the water channels are arranged on the upper surfaces of purlines in an erected mode, and the pressing bars on the left side and the right side of each photovoltaic module are fixedly connected with the corresponding water channel. Transverse connecting backing strips are mounted on the water channels, and the pressing bars at the upper ends and the lower ends of the photovoltaic modules are fixedly connected with the transverse connecting backing strips. The quick integration method comprises the steps that (1) the sealing adhesive tape is wrapped on the frameless photovoltaic modules; (2) the water channels are fixedly mounted on the upper surfaces of the purlines, and the transverse connecting backing strips are mounted on the water channels; (3) the photovoltaic modules are laid; (4) the photovoltaic modules are fixed. By the adoption of the integrated high-flatness solar power generation integral roof, the hidden danger of water leakage is avoided; by the adoption of the quick integration technology, the photovoltaic module frame packaging process is omitted, materials for packaging are saved, and the working efficiency is improved.

The invention discloses a packaging substrate as well as a manufacturing method and a base material thereof. The manufacturing method of the packaging substrate comprises the following steps: two metal layers are mutually laminated, and a dielectric layer is utilized to clad the two metal layers; next, layer increasing line structures are respectively formed at the two sides of the dielectric layer; and finally, the layer increasing line structures at the two sides of the dielectric layer are separated along the interface of the two metal layers so that two packaging substrates are formed. Inthe invention, the adhesion characteristics of the dielectric layer is utilized so that the two metal layers in the middle cannot be separated in the course of forming the layer increasing line structures in the initial stage, and the dielectric layer part around the two metal layers is cut off to successfully separate the two metal layers so that the manufacturing process is simplified, and the two metal layers in the middle can form a line layer, a metal lug or a supporting structure through the pattering manufacturing process and have no waste.