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Method of preparing groove semiconductor power device

A technology for power devices and semiconductors, which is applied in the field of preparation of trench semiconductor power discrete devices, can solve the problems of poor advantage index of semiconductor devices, poor terminal structure, and difficult to generate.

Inactive Publication Date: 2014-03-12
SHENZHEN LIZHEN SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In the existing trench power MOSFET design and manufacturing field, the base region and the source region of the MOSFET need to be introduced by the steps of base region mask and source region mask respectively. In order to reduce the manufacturing cost, some previous proposals, Such as an article published in the Japanese Journal of Applied Physics (Japanese Journal of Applied Physics Vol 47, No.3, 2008, pp.1507-1511), or US patent documents US20110233667, US20090085074, US20110233666, US077996427, etc., attempt to omit The device manufacturing method of the mask step of the base region or the source region, the steps are relatively complicated, it is not easy to generate, or its termination structure is not good, the breakdown voltage and reliability of the manufactured semiconductor device are relatively poor, or its source region The structure of the device is not good, so that the manufactured semiconductor device has a poor Figure of merit. The merit index is the low on-resistance of the device multiplied by the gate charge of the device

Method used

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  • Method of preparing groove semiconductor power device

Examples

Experimental program
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Embodiment 1

[0103] Such as figure 1 As shown, the p-type epitaxial layer 200 is first placed on the top of the n-type substrate 10, and then an oxide layer 400 (with a thickness of 0.3um to 1.5um oxide hard mask) is formed on the epitaxial layer by deposition or thermal growth. , depositing a layer of photoresist coating 1000 on the oxide layer, and then patterning through a trench mask to expose some parts of the oxide layer.

[0104] Such as figure 2 As shown, after dry etching the oxide layer exposed by patterning the trench mask, the epitaxial layer is exposed, and then the photolithographic coating is removed.

[0105] Such as image 3 As shown, trenches 300 (0.6um to 5.0um in depth and 0.12um to 1.5um in width) are formed by etching.

[0106] Such as Figure 4 As shown, after the trench is formed, the trench is sacrificially oxidized (the time is 10 minutes to 100 minutes, the temperature is 1000 ° C to 1200 ° C), in order to eliminate the silicon layer damaged by the plasma d...

Embodiment 2

[0123] It is an embodiment of the present invention.

[0124] Step and embodiment 1 are by Figure 1 to Figure 9 In the same way, a PSG oxide layer is formed on the surface of the silicon wafer and the top sidewall of the trench by deposition, with a thickness of 0.05um to 0.8um, and there is no need to form a non-doped oxide layer 501 on the surface of the silicon wafer and the top of the trench; Then planar etching or chemical mechanical polishing is performed on the oxide layer on the surface of the epitaxial layer to remove the PSG oxide layer on the surface of the epitaxial layer, and then a non-doped oxide layer is formed on the surface of the epitaxial layer by thermal growth or deposition. Layer, the thickness is 0.1um to 0.6um, remaining steps and embodiment 1 are by Figure 12 to Figure 19 same.

Embodiment 3

[0126] It is an embodiment of the present invention.

[0127] Step and embodiment 1 are by Figure 1 to Figure 12 In the same way, the N-type source region 203 is formed by using the source region mask step, and then the interlayer dielectric 503 is deposited on the surface of the epitaxial layer, and then the interlayer dielectric is eroded by using the contact hole mask to form an opening in the interlayer dielectric, Remaining steps and embodiment 1 are by Figure 16 to Figure 19 same.

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Abstract

The invention discloses a method for preparing a groove semiconductor power device, the method comprising the steps of first eroding a P-type epitaxial layer on an N-type substrate by use of a groove mask to form a plurality of grooves; forming a gate oxide layer on an inner side wall of each groove and filling each gate oxide layer with polysilicon; then forming a PSG oxide layer on a side wall at the top of each groove and diffusing an N-type dopant in each PSG oxide layer through high temperature into the epitaxial layer to form an N-type source region 202; then depositing an interlayer dielectric on the surface of the epitaxial layer; eroding the interlayer dielectric by use of a contact hole mask to form an opening in the interlayer dielectric and injecting an N-type dopant to form an N-type source region 203; eroding the surface of the epitaxial layer later to form a contact hole groove; carrying out metal plugging filling on the contact hole groove and depositing a metal layer on the surface of a device; and carrying out metal eroding by use of a metal mask to form a metal cushion layer and connection wires. By adopting the method of preparing the groove semiconductor power device, preparation procedures of base region masking and source region masking are eliminated, and the preparation cost of the device is greatly reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor power discrete devices, in particular to a preparation method of a trench-type semiconductor power discrete device. Background technique [0002] At present, power MOSFET (Metal Oxide Semiconductor Field Effect Transistor, Metal Oxide Semiconductor Field Effect Transistor) has been widely used in various electronic and communication products, computers, consumer appliances, automobiles, etc. At the same time, it also has various applications in industry. [0003] Power semiconductor devices represented by power MOSFETs can effectively control high-frequency large currents due to their low on-resistance and high-speed switching. At the same time, power MOSFETs are being widely used as small power conversion components such as power amplifiers, power converters, low noise amplifiers, and some personal computer power supply switches and power circuits, which are characterized by low power consu...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336
CPCH01L29/7397H01L29/7813
Inventor 苏冠创
Owner SHENZHEN LIZHEN SEMICON
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