A kind of preparation method of trench semiconductor power device

A power device and semiconductor technology, applied in the field of trench semiconductor power device preparation, can solve problems such as complex steps, poor device breakdown voltage and reliability, and poor terminal structure of semiconductor devices, so as to reduce manufacturing costs and increase performance and price Compared with the effect of omitting the preparation process

Inactive Publication Date: 2016-04-13
立新半导体有限公司
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In the existing field of design and manufacture of trench power MOSFETs, the base region and the source region of the MOSFET need to be introduced by the steps of base region mask and source region mask respectively, and some previously proposed, such as disclosed US patent documents US07799642, US20090085074, US20110233666, US20110233667, etc., try to omit the manufacturing method of the base region or source region or the base region and source region masking step, the steps are relatively complicated and difficult to generate, and the terminal structure of the manufactured semiconductor device is not good. Well, even the breakdown voltage and reliability of the device is relatively poor

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A kind of preparation method of trench semiconductor power device
  • A kind of preparation method of trench semiconductor power device
  • A kind of preparation method of trench semiconductor power device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0076] Such as figure 1 As shown, the N-type epitaxial layer is grown above the substrate. First, an oxide layer (hard oxide mask with a thickness of 0.3 μm to 1.5 μm) is formed on the epitaxial layer by deposition or thermal growth, and then deposited on the oxide layer. A photolithographic coating is then patterned through a trench mask to expose portions of the oxide layer.

[0077] Such as figure 2 As shown, after dry etching the oxide layer exposed by forming the pattern of the trench mask, the epitaxial layer is exposed, and a plurality of trench mask openings are formed on the oxide layer, and the opening width of the plurality of trench masks is different. Again, the width ranges from 0.2 μm to 2.0 μm, and then the photoresist coating is removed.

[0078] Such as image 3 As shown, implant P-type dopants on the surface of the device (the dose is 8e12 / cm 3 to 2e14 / cm 3 ), the part covered by the oxide layer is not implanted, and the part not covered by the oxide l...

Embodiment 2

[0090] Such as Figure 14a , 14b As shown, a thin oxide layer (padoxide with a thickness of 0.01 μm to 0.03 μm) is formed on the epitaxial layer by deposition or thermal growth, and a layer of polysilicon (0.5 μm to 1.2 μm in thickness) and a layer of polysilicon are deposited on it. layer silicon nitride (thickness 0.02μm to 0.2μm), such as Figure 15a As shown, a photoresist coating is deposited on the outermost surface, and then a part of the silicon nitride layer is exposed by patterning through a trench mask.

[0091] Such as Figure 15b As shown, after dry etching the part of the silicon nitride layer exposed by forming the pattern of the trench mask, dry etching is performed on the polysilicon exposed after the dry etching of the silicon nitride layer until the oxide pad layer under the polysilicon is exposed, The photoresist coating is then removed.

[0092] Such as Figure 16 As shown, implant P-type dopants on the surface of the device (the dose is 8e12 / cm 3 to...

Embodiment 3

[0107] The technical scheme of the present embodiment is roughly the same as that of embodiment 1, and its difference only lies in:

[0108] In the above example 1 Figure 7 Before etching the trench, deposit an oxide layer and seal the trench mask openings in the oxide layer with a width ranging from 0.2 μm to 0.6 μm. The sealed opening width can be 0.2 μm, Or 0.3μm or 0.4μm or 0.5μm or 0.6μm, depending on the preparation method. The advantage of this step is that some trench mask openings are implanted with P-type and N-type dopants but not opened. Out of the trench, the terminal structure of the device is better, so the breakdown voltage of the device is higher and more stable, and then the oxide layer is dry-etched to remove the oxide layer on the opening, exposing the epitaxial layer on the opening; At this time, only those openings that are not sealed by the precipitated oxide layer are opened. The trench (1.0μm to 7.0μm in depth and 0.2μm to 2.0μm in width) passes thro...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses a preparation method of a trench semiconductor power device. The preparation method of the trench semiconductor power device includes a first step of injecting dopant into an epitaxial layer arranged on a substrate for two times to form P-type base regions and N-type base regions, and conducting corrosion on the epitaxial layer to form a plurality of grid trenches; a second step of depositing interlayer mediums on the epitaxial layer, conducting the corrosion on the interlayer mediums through a contact hole mask, conducting the corrosion on the interlayer mediums and the surface of the epitaxial layer through a contact hole mask to form contact trenches, and conducting metal plugging filling on the contact trenches; and a third step of depositing a metal layer on the surface of the discrete device, conducting metal corrosion through a metal mask and forming a metal substrate layer and a connecting wire. The preparation method of the trench semiconductor power device eliminates preparation procedures of a base region mask and a source region mask, and therefore the manufacturing cost of the power device is greatly reduced. In addition, original electrical characteristics of the power device cannot be influenced. The cost-performance ratio of the power device is improved. The performance, the quality and the reliability of the trench semiconductor power device are not influenced.

Description

technical field [0001] The invention relates to the technical field of semiconductor power devices, in particular to a method for preparing a trench semiconductor power device. Background technique [0002] At present, the power MOSFET (MetalOxideSemiconductorFieldEffectTransistor, Metal Oxide Semiconductor Field Effect Transistor) has been widely used in various electronic and communication products, and at the same time, it also has various applications in industry. [0003] Power semiconductor devices represented by power MOSFETs can effectively control high-frequency large currents due to their low on-resistance and high-speed switching. At the same time, power MOSFETs are being widely used as small power conversion components such as power amplifiers, power converters, low noise amplifiers, and some personal computer power supply switches and power circuits, which are characterized by low power consumption and high speed. [0004] Trench power MOSFETs are widely used a...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336
Inventor 苏冠创
Owner 立新半导体有限公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap